| Patent application number | Description | Published |
|---|
| 20090033880 | MOBILE COMMUNICATION TERMINAL HAVING PROJECTOR - A radiation structure of a mobile communication terminal having a projector which rapidly dissipates heat generated from the projector and other elements built into the terminal. The mobile communication terminal includes a projector implementing an image-projection function, and a projector cover, which is composed of a heat conductive material such that at least one inner surface thereof is brought into close contact with the projector so as to dissipate heat generated from the projector to the outside of the terminal. | 02-05-2009 |
| 20090051750 | APPARATUS FOR WRITING IMAGE ON ELECTRONIC PAPER - Disclosed is an apparatus for writing an image on electronic paper, the apparatus including a writing head having a plurality of pixel electrodes corresponding to a plurality of pixels forming an image, the writing head applying a voltage to the pixel electrodes according to inputted address signals and data signals; a driver for generating the address and data signals according to an inputted image frame signal and outputting the address and data signals to the writing head; and a controller for generating the image frame signal and outputting the image frame signals to the driver. | 02-26-2009 |
| 20110025630 | CHARACTER RECOGNITION AND CHARACTER INPUT APPARATUS USING TOUCH SCREEN AND METHOD THEREOF - A character input method using a touch screen, in which one or more areas requiring user input is defined in the touch screen, pre-recognized information is defined for each of the defined areas, character information is received by a user in one or more user desired areas among the defined areas, the character information is recognized using a character recognizer, and the recognized character information is updated in the user desired areas. | 02-03-2011 |
| Patent application number | Description | Published |
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| 20090230456 | Semiconductor device - A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer. | 09-17-2009 |
| 20090302472 | Non-volatile memory devices including shared bit lines and methods of fabricating the same - Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts. | 12-10-2009 |
| 20100001366 | Semiconductor device having shared bit line structure and method of manufacturing the same - A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions. | 01-07-2010 |
| 20100008152 | SEMICONDUCTOR DEVICE INCLUDING DRIVING TRANSISTORS - A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region. | 01-14-2010 |
| 20100085812 | Nonvolatile Memory Devices Having Common Bit Line Structure - Provided is a nonvolatile memory device having a common bit line structure. The nonvolatile memory device includes multiple unit elements having a NAND cell array structure, arranged in each of multiple memory strings, and each including a control gate and a charge storage layer. Multiple common bit lines are each commonly connected to ends of each of one pair of memory strings among the memory strings. Provided are a first selection transistor having a first driving voltage and multiple second selection transistors connected in series to the first selection transistors and having a second driving voltage that is lower than the first driving voltage. The first selection transistor and the second selection transistors are arranged between the common bit lines and the unit elements of the of memory strings. A first string selection line is connected to one of the first and second selection transistors of a first memory string of one pair of memory strings that are connected to one of the common bit lines. A second string selection line is connected to one of the first and second selection transistors of a second memory string of one pair of memory strings that are connected to one of the common bit lines. Multiple word lines are connected to control gates of the unit elements having the NAND cell array structure which are arranged in the same rows. | 04-08-2010 |
| 20110140202 | FLASH MEMORY DEVICE HAVING TRIPLE WELL STRUCTURE - A flash memory device, including a cell array region where a plurality of memory cells are connected in series to a single cell string, the cell array region including a pocket p-well configured to accommodate the plurality of memory cells and an n-well configured to surround the pocket p-well, a first peripheral region where low-voltage (LV) and high-voltage (HV) switches are connected to the memory cells through a word line, and a second peripheral region where bulk voltage switches are connected to bulk regions of the LV and HV switches. | 06-16-2011 |
