| Patent application number | Description | Published |
|---|
| 20080248637 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In one embodiment, a gate insulating layer, a conductive layer, and a metal layer are formed over a semiconductor substrate. An ion implantation region is formed in an interface of the conductive layer and the metal layer by performing an ion implantation process. A flash annealing process is performed on the ion-implanted semiconductor substrate. The metal layer, the conductive layer, and the gate insulating layer are patterned. | 10-09-2008 |
| 20090018035 | Packages, biochip kits and methods of packaging - A package having an improved yield is provided. The package includes a support on which a plurality of biochips are disposed, and a cover bonded to the support and defining a reaction space for each of the plurality of biochips together with the support, the cover including at least one inlet/outlet. | 01-15-2009 |
| 20090032966 | Method of fabricating a 3-D device and device made thereby - A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern. | 02-05-2009 |
| 20090109642 | SEMICONDUCTOR MODULES AND ELECTRONIC DEVICES USING THE SAME - Semiconductor devices and electronic devices using the same. The semiconductor module may include a first semiconductor chip, and a module substrate having a top surface on which the first semiconductor chip is mounted and a second surface opposite the top surface, wherein the module substrate includes a first buffer layer to relieve stress occurring due to a difference of thermal expansions between the first semiconductor chip and the module substrate. | 04-30-2009 |
| 20090111217 | Method of manufacturing chip-on-chip semiconductor device - Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device with a metal wiring having at least one discontinuous spot formed therein, preparing a second semiconductor device with at least one bump formed on a surface of the second semiconductor device corresponding to the at least one discontinuous spot, aligning the first semiconductor device onto the second semiconductor device, and connecting the at least one bump of the second semiconductor device to the at least one discontinuous spot formed in the metal wiring of the first semiconductor device. | 04-30-2009 |
| 20090111233 | METHOD OF FORMING JUNCTION OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming junctions of a semiconductor device. According to the method of forming junctions of a semiconductor device in accordance with an aspect of the present invention, there is provided a semiconductor substrate in which a transistor including the junctions are formed. A first thermal treatment process for forming a passivation layer over the semiconductor substrate including the junctions is performed. Here, the passivation layer functions to prevent impurities within the junctions from being drained. A pre-metal dielectric layer is formed over the semiconductor substrate including the passivation layer. | 04-30-2009 |
| 20090184411 | SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME - Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure. | 07-23-2009 |
| 20090186780 | Biochip - A biochip for qualitatively analyzing a biological sample using probes includes a probe cell array comprising a plurality of probe cells capable of coupling with biomolecules of a biological sample, an optical sensor for detecting optical signals from probe cells selectively coupling with the biomolecules of the biological sample and converting the optical signals to digital electrical signals, and a memory cell array for storing the digital electrical signals. | 07-23-2009 |
| 20090215229 | Board on chip package and method of manufacturing the same - A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening. | 08-27-2009 |
| 20090302418 | FUSE STRUCTURE OF A SEMICONDUCTOR DEVICE - Provided is a fuse structure of a semiconductor device. The fuse structure may include an insulating layer pattern structure, a fuse and a protecting layer pattern. The insulating layer pattern structure may be formed on a substrate. The insulating layer pattern structure may have an opening. The fuse may be formed in the opening. The protecting layer pattern may be formed in the opening of the insulating layer pattern structure to cover the fuse. | 12-10-2009 |
| 20100032807 | Wafer level semiconductor module and method for manufacturing the same - A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas. | 02-11-2010 |
| 20100108865 | SUBSTRATE FOR DETECTING SAMPLES, BIO-CHIP EMPLOYING THE SUBSTRATE, METHOD OF FABRICATING THE SUBSTRATE FOR DETECTING SAMPLES, AND APPARATUS FOR DETECTING BIO-MATERIAL - A substrate for detecting samples includes; a body, and a plurality of micro lenses arranged on the body and configured for attachment to at least one sample, wherein the at least one sample emits fluorescent light, and wherein the plurality of micro lenses condense the fluorescent light emitted from the at least one sample via refraction. | 05-06-2010 |
| 20100173798 | BIOCHIP IN WHICH HYBRIDIZATION CAN BE MONITORED, APPARATUS FOR MONITORING HYBRIDIZATION ON BIOCHIP AND METHOD OF MONITORING HYBRIDIZATION ON BIOCHIP - A biochip for monitoring hybridization is provided. The biochip includes a transparent substrate and a first probe region. The first probe region is disposed on the transparent substrate and has a plurality of analytical probes. The plurality of analytical probes are configured to bond to a sample having a fluorescence material. The plurality of analytical probes are used in analyzing the sample using fluorescence detection. The biochip further includes a second probe region disposed on the transparent substrate and having a plurality of monitoring probes used in monitoring hybridization according to a surface plasmon resonance in the second probe region. The biochip further includes a thin metal layer disposed between the second probe region and the transparent substrate. | 07-08-2010 |
| 20100207278 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure is disclosed. The semiconductor package structure includes semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias extend through each of the semiconductor chips. Redistribution structures and a chip selection interconnection line are disposed on each of the semiconductor chips. The redistribution structures electrically connect at least one of the through-vias with at least one of the chip pads. Each chip selection interconnection line includes first regions connected to a corresponding number of the through-vias and a second region connecting at least one of the first regions with one of the chip pads. The semiconductor chips are stacked and electrically connected using the through-vias. | 08-19-2010 |
| 20110014748 | Semiconductor packages, stacked semiconductor packages, and methods of manufacturing the semiconductor packages and the stacked semiconductor packages - A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate. | 01-20-2011 |
