Patent application number | Description | Published |
20090117710 | METHOD OF CUTTING SEMICONDUCTOR WAFER, SEMICONDUCTOR CHIP APPARATUS, AND CHAMBER TO CUT WAFER - A method of cutting a semiconductor wafer includes preparing a semiconductor wafer including a scribe region and a chip region, forming a groove in the scribe region, loading the semiconductor wafer with the groove formed therein in a chamber, and cutting the semiconductor wafer into a plurality of chips through increasing a pressure of the chamber by a first pressure change rate, and then reducing the pressure of the chamber by a second pressure change rate. | 05-07-2009 |
20090168382 | SEMICONDUCTOR MODULE - A semiconductor module can include a printed circuit board (PCB) and a semiconductor package inserted into an inner space of the PCB. The semiconductor package may be electrically connected to the PCB. The PCB may thus surround the semiconductor package so that cracks may not be generated in the outer terminals. | 07-02-2009 |
20090184418 | WIRING SUBSTRATE, TAPE PACKAGE HAVING THE SAME, AND DISPLAY DEVICE HAVING THE SAME - A wiring substrate includes a base film, a plurality of first wirings and a plurality of second wirings. The base film has a chip-mounting region configured for mounting a semiconductor chip thereon. The first wirings extend in a first direction from inside the chip-mounting region to outside the chip-mounting region, and include first connection end portions extending in a second direction different from the first direction. The first connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip. The second wirings extend in the first direction from inside the chip-mounting region to outside the chip-mounting region, and include second connection end portions extending in the opposite direction to the second direction in which the first connection end portions extend, and the second connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip. | 07-23-2009 |
20090189274 | TAPE WIRING SUBSTRATE AND TAPE PACKAGE USING THE SAME - A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern. | 07-30-2009 |
20100000767 | Tab tape for tape carrier package - A TAB tape for a tape carrier package may have at least one opening formed in a connection portion. The at least one opening may be provided in the connection portion and a portion of the corresponding second lead. The at least one opening may be arranged near a boundary between the corresponding first lead and the connection portion. The at least one opening may be sized to reduce the change of the lead width from the first lead to the second lead. | 01-07-2010 |
20100001392 | Semiconductor package - Provided is a semiconductor package including a substrate and a semiconductor chip formed on the substrate. The semiconductor chip may include a chip alignment mark on a surface of the semiconductor chip, and wiring patterns formed on a surface of the substrate, wherein the chip alignment mark is bonded to the wiring patterns. Accordingly, the surface area of the semiconductor chip may be reduced. | 01-07-2010 |
20100005652 | Method of manufacturing a wiring substrate, method of manufacturing a tape package and method of manufacturing a display device - Disclosed is a method of manufacturing a wiring substrate, a tape package using the wiring substrate, and a display device using the wiring substrate. In a method of manufacturing a wiring substrate, a screen may be disposed on a base plate, the screen having openings for forming wirings. A conductive paste may be coated in the openings of the screen. A substrate may be on the screen, the conductive paste being coated in the openings of the screen. The conductive paste may be hardened to be adhered to the substrate. The base plate and the screen may be removed from the substrate to form wirings on the substrate. Because the wirings may be formed using a glass substrate having heat-resisting properties by simplified processes, thermal deflections of the substrate and dimension variations in manufacturing processes may be reduced or minimized. | 01-14-2010 |
20100038438 | UNIVERSAL PCB AND SMART CARD USING THE SAME - A smart card is provided including a body with a cavity, an IC chip inserted into the cavity, and a universal PCB on which the IC chip can be mounted and electrically contacted regardless of its size, type and bonding structure. The universal PCB comprises groups of contact pads suitable for contacting IC chips of different sizes and designs. | 02-18-2010 |
20100187686 | SEMICONDUCTOR PACKAGE COMPRISING ALIGNMENT MEMERS - A semiconductor package comprising alignment members is provided. The semiconductor package includes a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate including a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals. The semiconductor package further includes a first alignment member disposed on the first surface of the semiconductor die, and a second alignment member disposed on the substrate portion of the tape substrate and disposed corresponding to the first alignment member. | 07-29-2010 |
20110006442 | SEMICONDUCTOR CHIP, FILM SUBSTRATE, AND RELATED SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip. | 01-13-2011 |
20110169148 | TAPE WIRING SUBSTRATE AND TAPE PACKAGE USING THE SAME - A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern. | 07-14-2011 |
20110233755 | Semiconductor Housing Package, Semiconductor Package Structure Including The Semiconductor Housing Package, And Processor-Based System Including The Semiconductor Package Structure - A semiconductor housing package may be provided. The semiconductor housing package may include a mold layer, a housing chip, a redistribution structure, and a housing node. The mold layer may surround and partially expose the housing chip. The redistribution structure may be electrically connected to the housing chip and may be disposed on the mold layer. The housing node may be in contact with the redistribution structures. The semiconductor housing package may be disposed on a semiconductor base package and may constitute a semiconductor package structure along with the semiconductor base package. The semiconductor package structure may be disposed on a processor-based system. | 09-29-2011 |
20120068349 | TAPE PACKAGE - A tape package providing a plurality of input and output portions each having a minimum pitch. The tape package includes a tape wiring substrate including first and second wirings, and a semiconductor chip mounted on the tape wiring substrate, and including a first edge, a first pad disposed adjacent to the first edge, and a second pad disposed to be farther spaced apart from the first edge than the first pad, where the first wiring is connected to a portion of the first pad that is spaced from the first edge by a first distance, and where the second wiring is connected to a portion of the second pad that is spaced from the first edge by a second distance that is greater than the first distance. | 03-22-2012 |
20120105089 | SEMICONDUCTOR PACKAGE HAVING TEST PADS ON TOP AND BOTTOM SUBSTRATE SURFACES AND METHOD OF TESTING SAME - A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto. | 05-03-2012 |
20140084442 | Semiconductor Packages Having a Guide Wall and Related Systems and Methods - A semiconductor package includes a first package board, a first semiconductor chip arranged on the first package board, a heat transfer layer arranged on the first semiconductor chip, a heat spreader arranged on the heat transfer layer, and a housing having a molding part arranged on the first package board and directly surrounding side surfaces of the first semiconductor chip and a guide wall arranged on the molding part, with the guide wall spaced apart from the heat spreader and surrounding side surfaces of the heat spreader. | 03-27-2014 |
20140117536 | WIRING SUBSTRATE, TAPE PACKAGE HAVING THE SAME, AND DISPLAY DEVICE HAVING THE SAME - A wiring substrate includes a base film, a plurality of first wirings and a plurality of second wirings. The base film has a chip-mounting region configured for mounting a semiconductor chip thereon. The first wirings extend in a first direction from inside the chip-mounting region to outside the chip-mounting region, and include first connection end portions extending in a second direction different from the first direction. The first connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip. The second wirings extend in the first direction from inside the chip-mounting region to outside the chip-mounting region, and include second connection end portions extending in the opposite direction to the second direction in which the first connection end portions extend, and the second connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip. | 05-01-2014 |