Patent application number | Description | Published |
20130267042 | MRAM Fabrication Method with Sidewall Cleaning - Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described. | 10-10-2013 |
20130334633 | Magnetic Tunnel Junction With Non-Metallic Layer Adjacent to Free Layer - A spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack includes layers to which when electric current is applied cause switching of the direction of magnetization of at least one of the layer. The STTMRAM MTJ stack includes a reference layer (RL) with a direction of magnetization that is fixed upon manufacturing of the STTMRAM MTJ stack, a junction layer (JL) formed on top of the RL, a free layer (FL) formed on top of the JL. The FL has a direction of magnetization that is switchable relative to that of the RL upon the flow of electric current through the spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack. The STTMRAM MTJ stack further includes a spin confinement layer (SCL) formed on top of the FL, the SCL made of ruthenium. | 12-19-2013 |
20130341801 | Redeposition Control in MRAM Fabrication Process - Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode. | 12-26-2013 |
20140042567 | MTJ MRAM WITH STUD PATTERNING - Use of a multilayer etching mask that includes a stud mask and a removable spacer sleeve for MTJ etching to form a bottom electrode that is wider than the rest of the MTJ pillar is described. The first embodiment of the invention described includes a top electrode and a stud mask. In the second and third embodiments the stud mask is a conductive material and also serves as the top electrode. In embodiments after the stud mask is formed a spacer sleeve is formed around it to initially increase the masking width for a phase of etching. The spacer is removed for further etching, to create step structures that are progressively transferred down into the layers forming the MTJ pillar. In one embodiment the spacer sleeve is formed by net polymer deposition during an etching phase. | 02-13-2014 |
20140138609 | HIGH DENSITY RESISTIVE MEMORY HAVING A VERTICAL DUAL CHANNEL TRANSISTOR - Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F | 05-22-2014 |
20140170776 | MTJ STACK AND BOTTOM ELECTRODE PATTERNING PROCESS WITH ION BEAM ETCHING USING A SINGLE MASK - Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step. | 06-19-2014 |
20150014800 | MTJ MEMORY CELL WITH PROTECTION SLEEVE AND METHOD FOR MAKING SAME - Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment of the present invention as applied to a memory cell comprises a top electrode layer, an upper magnetic layer, a barrier layer, a lower magnetic layer and a bottom electrode layer in a pillar formed on a landing pad; and a sleeve of dielectric material generally surrounding sidewalls of at least the barrier layer and the lower magnetic layer and partially surrounding the bottom electrode layer. The bottom electrode layer includes a ledge that extends under the sleeve of dielectric material and separates the sleeve of dielectric material from the landing pad under the bottom electrode layer. | 01-15-2015 |
20150014801 | Redeposition Control in MRAM Fabrication Process - Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode. | 01-15-2015 |