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Dong Gyu Lee
Dong Gyu Lee, Suwon KR
| Patent application number | Description | Published |
|---|---|---|
| 20110079926 | Method of manufacturing substrate for flip chip and substrate for flip chip manufactured using the same - There is provided a method of manufacturing a substrate for flip chip, and a substrate for flip chip manufactured using the same. The method includes providing a base substrate including at least one conductive pad, forming a solder resist layer on the base substrate, the solder resist layer including a first opening exposing the conductive pad, forming a dry film on the solder resist layer, the dry film including a second opening connected with the first opening, forming a metal post in the first opening and a part of the second opening, filling the second opening above the metal post with solder paste, forming a solder cap by performing a reflow process on the filled solder paste, planarizing a surface of the solder cap, and removing the dry film. Accordingly, fine pitches and improve reliability can be achieved. | 04-07-2011 |
| 20110133332 | Package substrate and method of fabricating the same - There is provided a package substrate allowing for enhanced reliability by improving the structure of a solder bump and a method of fabricating the same. The package substrate includes: a substrate having at least one conductive pad; an insulating layer provided on the substrate and having an opening to expose the conductive pad; a post terminal provided on the conductive pad inside the opening; and a solder bump provided on the post terminal and having an angle between a bottom surface and a side surface thereof ranging from 80° to 120°. | 06-09-2011 |
Dong Gyu Lee, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090087950 | Wafer packaging method - A wafer packaging method is disclosed. | 04-02-2009 |
| 20090205854 | Printed circuit board for a package and manufacturing method thereof - A printed circuit board for use in a package and to a method of manufacturing the printed circuit board. The method of manufacturing the printed circuit board can include: providing a substrate, on one side of which at least one solder pad and at least one guide pad are formed; forming a solder resist layer over the one side of the substrate; uncovering at least one portion of the solder resist layer such that the guide pad is exposed; applying a surface treatment on the exposed guide pad; uncovering at least one portion of the solder resist layer such that the solder pad is exposed; and forming a solder bump on the exposed solder pad. With this method, the amount of surface treatment applied can be minimized, for reduced costs, and the occurrence of undiffused layers can be avoided, for improved reliability in the final product. | 08-20-2009 |
| 20100044084 | Printed circuit board and method of manufacturing the same - Provided is a printed circuit board (PCB) including a substrate that has a pad formed thereon; solder resist that is disposed on the substrate so as to expose the pad; a post that is disposed on the post; a surface-treatment layer that is disposed on the post; and a bump that is disposed on the surface-treatment layer. | 02-25-2010 |
| 20100270067 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - A printed circuit board and a method of manufacturing the printed circuit board are disclosed. In accordance with an embodiment of the present invention, the method includes providing a substrate having a pad formed thereon, forming a resist on the substrate, in which the resist has an opening formed therein such that the pad is exposed, forming a metal post inside the opening such that the metal post is electrically connected to the pad, forming a through-hole in the resist by removing a portion of the resist such that the through-hole surrounds the metal post, and forming a solder layer inside the through-hole and on an upper surface of the metal post so as to cover an exposed surface of the metal post. | 10-28-2010 |
| 20110014827 | Lead pin for package substrate - Disclosed herein is a lead pin for a package substrate. | 01-20-2011 |
Dong Gyu Lee, Gyunggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100132998 | Substrate having metal post and method of manufacturing the same - The invention relates to a substrate having a metal post and a method of manufacturing the same, in which a round solder bump part formed on a metal post melts and flows down along a lateral surface of the metal post by being subjected twice to a reflow process, thus forming a solder bump film for preventing oxidation and corrosion of the metal post. | 06-03-2010 |
| 20100314161 | SUBSTRATE FOR FLIP CHIP BONDING AND METHOD OF FABRICATING THE SAME - Disclosed is a substrate for flip chip bonding, in which a base solder layer is formed between a pad and a metal post, thereby increasing impact resistance and mounting reliability. A method of fabricating the substrate for flip chip bonding is also provided. | 12-16-2010 |
Dong Gyu Lee, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090299666 | Fourier Transform-Based Phasor Estimation Method and Apparatus Capable of Eliminating Influence of Exponentially Decaying DC Offsets - Disclosed herein is a Fourier transform-based phasor estimation method and apparatus capable of eliminating the S influence of exponentially decaying DC offsets. According to a Fourier transform-based phasor estimation method according to an embodiment of the present invention, an input signal is sampled, and samples of one-cycle data of the input signal are separated into at least two sample groups. A Discrete Fourier Transform (DFT) is performed on each of the sample groups. A DC offset included in the input signal is calculated on a basis of results of the DFT on each of the sample groups, and an error caused by the DC offset is calculated using the calculated DC offset. A phasor of a fundamental frequency component included in the input signal is estimated by eliminating the calculated error, caused by the DC offset, from the results of the DFT on the input signal. | 12-03-2009 |