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Dong-Chan
Dong Chan Kim, Daejeon KR
| Patent application number | Description | Published |
|---|---|---|
| 20090138743 | METHOD AND APPARATUS FOR SECURE COMMUNICATION BETWEEN CRYPTOGRAPHIC SYSTEMS USING REAL TIME CLOCK - Provided are a method and apparatus for secure communication between cryptographic systems using a Real Time Clock (RTC). The method and apparatus allow a transmitting cryptographic system to transfer partial RTC data and a receiving cryptographic system to restore entire RTC data, thereby minimizing data to be transferred between the cryptographic systems. The method includes: calculating a largest RTC deviation between a transmitting cryptographic system and a receiving cryptographic system; calculating the smallest number of bits of partial data on an RTC required for restoring entire data on the RTC on the basis of the calculated largest RTC deviation; calculating the partial RTC data on the basis of the calculated smallest number of bits of the partial RTC data; and transferring the calculated partial RTC data to the receiving cryptographic system. | 05-28-2009 |
Dong Chan Park, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20120013418 | APPARATUS AND METHOD FOR DETECTING TRANSMISSION AND RECEPTION SIGNAL - Provided is a transmission and reception signal detecting apparatus, which includes a directional coupler and a signal detecting part. The directional coupler includes a first port and a second port. The signal detecting part is connected to the first and second ports of the directional coupler and detects an output of a first signal transmitted through the first port and an output of a second signal transmitted through the second port. The signal detecting part is connected to the first port under a first operation condition. The signal detecting part is connected to the second port under a second operation condition. | 01-19-2012 |
Dong Chan Shin, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20110190034 | MOBILE TERMINAL AND METHOD FOR DISPLAYING INFORMATION - Disclosed herein are a mobile terminal and a method for displaying information using the same. A mobile terminal includes a display unit that displays information or applications processed in the mobile terminal on a display panel; and a control unit that controls the information or applications displayed on the display unit to be rotated at an angle with respect to the display panel and controls additional information or applications to be displayed on portions about the displayed information or applications produced by the rotation if a reference signal is inputted to the mobile terminal. | 08-04-2011 |
Dong-Chan Kim, Anyang-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110124172 | METHOD OF FORMING INSULATING LAYER AND METHOD OF MANUFACTURING TRANSISTOR USING THE SAME - Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO | 05-26-2011 |
| 20110237037 | Methods of Forming Recessed Channel Array Transistors and Methods of Manufacturing Semiconductor Devices - In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure. | 09-29-2011 |
Dong-Chan Kim, Seoul-City KR
| Patent application number | Description | Published |
|---|---|---|
| 20100055914 | METHODS OF FORMING FINE PATTERNS IN SEMICONDUCTOR DEVICES - Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths. | 03-04-2010 |
Dong-Chan Kim, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100025749 | SEMICONDUCTOR DEVICE - A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes. The insulating interlayer may have a contact hole between the gate electrodes. The impurity region may be in the substrate exposed through the contact hole. The capping layer may be on the impurity region. The plug may be on the capping layer. Thus, the impurities may not be lost from the impurity region. As a result, the device may have improved electrical characteristics and reliability because depletion may not be generated in the electrode layer | 02-04-2010 |
| 20100035425 | Integrated Circuit Devices Having Partially Nitridated Sidewalls and Devices Formed Thereby - Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer. | 02-11-2010 |
| 20100072545 | Recessed Channel Array Transistors, and Semiconductor Devices Including a Recessed Channel Array Transistor - A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current. | 03-25-2010 |
Dong-Chan Kim, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090233416 | FLASH MEMORY DEVICES COMPRISING PILLAR PATTERNS AND METHODS OF FABRICATING THE SAME - Flash memory devices include pillar patterns formed between selected pairs of floating gates and control gate extensions that penetrate between selected pairs of floating gates are provided. Methods of fabricating the flash memory devices are also provided. | 09-17-2009 |
| 20100109057 | Fin field effect transistor and method of fabricating the same - A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode. | 05-06-2010 |
| 20100155959 | Semiconductor Devices Having Narrow Conductive Line Patterns and Related Methods of Forming Such Semiconductor Devices - Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction. | 06-24-2010 |
Dong-Chan Lim, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090256177 | Semiconductor device including an ohmic layer - In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance. | 10-15-2009 |
Dong-Chan Lim, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100250675 | SYSTEM AND METHOD FOR TRANSMITTING PERSONAL NETWORKING-BASED BLOG POST, AND SERVER APPLIED TO THE SAME - Disclosed are a system and method for distributing a blog post based on personal networking, and a server to be applied thereto. The system includes a writer terminal unit, which makes a series of settings for forming a blog post containing contents posted by a writer through the writer's blog registered with an online community service, and then distributes the blog post to at least one or more acquaintances blogs registered to personal networking with the writer, sharer/distributor terminal units, which make setting for posting the blog post on the acquaintances blogs, or distributing the blog post to at least one or more other acquaintances blogs registered to personal networking with sharers/distributors, and a service management server, which differentially provides management authority for the blog post to each of the writer and the sharers/distributors, and integrally manages the blog post distributed to a plurality of blogs, based on a path along which the blog post is distributed. The system and method distributes a blog post containing a writer's specific purpose of posting, such as a help-wanted notice, step by step through blogs registered with an online community service, based on trust relationships, thereby providing a notice platform, which is so efficient that an advertiser who writes a blog post, such as a help-wanted notice, can quickly find a qualified person, based on his/her trust relationships. | 09-30-2010 |