| Patent application number | Description | Published |
|---|
| 20080222430 | Protection of Secure Electronic Modules Against Attacks - A method and apparatus is disclosed for preventing the unintended retention of secret data caused by preferred state/burn in secure electronic modules. Sequentially storing the data, and its inverse on alternating clock cycles, and by actively overwriting it to destroy it, prevents SRAM devices from developing a preferred state. By encrypting a relatively large amount of secret data with a master encryption key, and storing said master key in this non-preferred state storage, the electronic module conveniently extends this protection scheme to a large amount of data, without the overhead of investing or actively erasing the larger storage area. | 09-11-2008 |
| 20080247245 | WRITE CONTROL METHOD FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE MEMORY SUBARRAYS - Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal. | 10-09-2008 |
| 20080263417 | Efficient Memory Product for Test and Soft Repair of SRAM with Redundancy - Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief. | 10-23-2008 |
| 20090034345 | Eight Transistor SRAM Cell with Improved Stability Requiring Only One Word Line - An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell. | 02-05-2009 |
| 20100001696 | SYSTEM TO IMPROVE A MULTISTAGE CHARGE PUMP AND ASSOCIATED METHODS - A system to improve a multistage charge pump may include a capacitor, a first plate carried by the capacitor, and a second plate carried by the capacitor opposite the first plate. The system may also include a clock to control charging and discharging of the capacitor. The system may further include a power supply to provide a power supply voltage across the first plate and the second plate during charging of the capacitor. The system may also include a voltage line to lift the second plate to an intermediate voltage during discharging of the capacitor. The system may further include an output line connected to the first plate during discharging of the capacitor to provide an output voltage. | 01-07-2010 |
| 20100001709 | SYSTEM TO GENERATE A REFERENCE FOR A CHARGE PUMP AND ASSOCIATED METHODS - A system to generate a reference for a charge pump may include a diode-connected transistor providing a reference voltage, and an output transistor. The system may also include a reference circuit to provide a current that is substantially temperature insensitive and the reference circuit delivers the current across the diode-connected transistor thereby enabling the reference voltage to move with processing of the diode-connected transistor. | 01-07-2010 |
| 20100002478 | SYSTEM TO IMPROVE A VOLTAGE MULTIPLIER AND ASSOCIATED METHODS - A system to improve a voltage multiplier may include a voltage multiplier circuit, and a capacitor carried by the multiplier circuit. The system may also include a transistor to charge an up voltage of the capacitor. | 01-07-2010 |
| 20100268880 | Dynamic Runtime Modification of Array Layout for Offset - Disclosed are a method, a system and a computer program product for operating a cache system. The cache system can include multiple cache lines, and a first cache line of the multiple of cache lines can include multiple cache cells, and a bus coupled to the multiple cache cells. In one or more embodiments, the bus can include a switch that is operable to receive a first control signal and to split the bus into first and second portions or aggregate the bus into a whole based on the first control signal. When the bus is split, a first cache cell and a second cache cell of the multiple cache cells are coupled to respective first and second portions of the bus. Data from the first and second cache cells can be selected through respective portions of the bus and outputted through a port of the cache system. | 10-21-2010 |
