| Patent application number | Description | Published |
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| 20100323485 | PN JUNCTION AND MOS CAPACITOR HYBRID RESURF TRANSISTOR - A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate with a drift region between source region and drain regions. The drift region includes a structure having a spaced trench capacitor extending between the source region and the drain region and a vertical stack extending between the source region and the drain region. When the device is in an on state, current flows between the source and drain regions; and, when the device is in an off/blocking state, the drift region is depleted into the stack. | 12-23-2010 |
| 20110014760 | Method of Forming Lateral Trench Gate FET with Direct Source-Drain Current Path - A method of forming a field effect transistor (FET) includes: forming a drift region comprising a stack of alternating conductivity type silicon layers; forming a drain region of a first conductivity type extending into the stack of alternating conductivity type silicon layers; forming a trench gate extending into the stack of alternating conductivity type silicon layers, the trench gate having a non-active sidewall and an active sidewall being perpendicular to one another; and forming a body region of a second conductivity type adjacent to the active sidewall of the trench gate, wherein the trench gate and the drain region are formed such that the non-active sidewall of the trench gate faces the drain region. | 01-20-2011 |
| 20110127601 | Semiconductor Devices and Methods for Making the Same - Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described. | 06-02-2011 |
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| 20080199997 | Methods of Forming Inter-poly Dielectric (IPD) Layers in Power Semiconductor Devices - A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities. | 08-21-2008 |
| 20090230465 | Trench-Gate Field Effect Transistors and Methods of Forming the Same - A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region. | 09-17-2009 |
| 20100237415 | Semiconductor Power Device Having a Top-side Drain Using a Sinker Trench - A semiconductor power device includes a plurality of groups of stripe-shaped trenches extending in a silicon region over a substrate, and a contiguous sinker trench completely surrounding each group of the plurality of stripe-shaped trenches so as to isolate the plurality of groups of stripe-shaped trenches from one another. The contiguous sinker trench extends from a top surface of the silicon region through the silicon region and terminates within the substrate. The contiguous sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the contiguous sinker trench makes electrical contact with the substrate along the bottom of the contiguous sinker trench and makes electrical contact with an interconnect layer along the top of the contiguous sinker trench. | 09-23-2010 |
| 20100258862 | TRENCH-GATE FIELD EFFECT TRANSISTOR WITH CHANNEL ENHANCEMENT REGION AND METHODS OF FORMING THE SAME - A field effect transistor includes a body region of a first conductivity type in a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminating within the semiconductor region. A source region of the second conductivity type extends in the body region adjacent the gate trench. The source region and an interface between the body region and the semiconductor region define a channel region therebetween which extends along the gate trench sidewall. A channel enhancement region of the second conductivity type is formed adjacent the gate trench. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region. | 10-14-2010 |
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| 20090111231 | Method for Forming Shielded Gate Field Effect Transistor Using Spacers - A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed. | 04-30-2009 |
| 20090302327 | RUGGED SEMICONDUCTOR DEVICE ARCHITECTURE - A wide bandgap silicon carbide device has an avalanche control structure formed in an epitaxial layer of a first conductivity type above a substrate that is connected to a first electrode of the device. A first region of a second conductivity type is in the upper surface of the epitaxial layer with a connection to a second electrode of the device. A second region of the first conductivity type lies below the first region and has a dopant concentration greater than the dopant concentration in the epitaxial layer. | 12-10-2009 |
| 20100155839 | LATERAL MOSFET WITH SUBSTRATE DRAIN CONNECTION - In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region. In another form the lateral MOSFET includes a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body. | 06-24-2010 |
