| Patent application number | Description | Published |
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| 20090113263 | METHODS FOR ANALYZING SCAN CHAINS, AND FOR DETERMINING NUMBERS OR LOCATIONS OF HOLD TIME FAULTS IN SCAN CHAINS - In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain. The number of possible hold time faults in the scan chain can be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain. If a value of the environmental variable at which the scan chain operates correctly can be determined, the location of one or more hold time faults can also be determined. | 04-30-2009 |
| 20090113265 | LOCATING HOLD TIME VIOLATIONS IN SCAN CHAINS BY GENERATING PATTERNS ON ATE - A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain. | 04-30-2009 |
| 20100031092 | METHOD FOR OPERATING A SECURE SEMICONDUCTOR IP SERVER TO SUPPORT FAILURE ANALYSIS - A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components. | 02-04-2010 |
| Patent application number | Description | Published |
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| 20080259078 | Apparatus and Method for Determining Intersections - In a data processing system for determining intersections between geometric objects, the work is split between a CPU and a stream processor. The intersection determination is controlled by the CPU. Data processing intensive parts of intersection algorithms, such as checking possible overlap of objects, checking overlap of normal fields of objects, approximating the extent of an object, approximating the normal fields of an object, or making conjectures for intersection topology and/or geometry between objects, are run on the stream processor. The results of the algorithmic parts run on the stream processor are used by the part of the algorithms run on the CPU. In cases where conjectures for the computational result are processed on the stream processor, the conjectures are checked for correctness by algorithms run on the CPU. If the correctness check shows that the result found is incomplete or wrong, additional parts of the algorithm are run on the CPU and possibly on the stream processor. | 10-23-2008 |
| 20090164756 | Geological Response Data Imaging With Stream Processors - The invention describes a method to convert geological response data to graphical raw data by using at least one stream processor for this purpose. The geological response data is pre-processed by a CPU and the preprocessed geological response data is fed into one or more stream processors. The stream processor then does the calculation intensive work on the preprocessed geological response data and returns the processing results back to the CPU which does some post-processing on the results coming from the stream processor Stream processors comprise single or multiple programmable GPUs, clusters/networks of nodes with one or several GPU's; cell processors (or processors derived from it) or a cluster of cell processor nodes, game computers (in the spirit of Sony's PlayStation, Nintendo's GameCube, etc.) or clusters of game computers. | 06-25-2009 |
| 20090213144 | APPARATUS AND METHOD TO CALCULATE RASTER DATA - A computer apparatus is disclosed for determining high quality raster data generation of scalar fields or vector fields, represented by piecewise polynomials or piecewise rational functions. It comprise one or more CPUs operative to do portions of the raster data generation algorithm, initializing sub-algorithms thereof, control the sub-algorithms, and possibly read back the generated raster data or transfer the raster data to other processors in the system. The computer apparatus further comprises one or more stream processing units operative to receive parts of the raster data algorithm from the CPUs and to execute sub-algorithms of the raster data algorithm, resulting in raster data that can be directly visualized, read back to the CPU or transferred to other processors. | 08-27-2009 |
