| Patent application number | Description | Published |
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| 20080301528 | Method and apparatus for controlling memory - A memory control apparatus includes a reading unit, an inserting unit, an identifying unit, a determining unit, and an outputting unit. The reading unit reads data from the memory. The inserting unit inserts a dummy error at an insertion position in the data thereby obtaining error data. The identifying unit identifies an error position at which an error has occurred in the error data. The determining unit determines whether the insertion position matches the error position. When the insertion position matches the error position, the outputting unit outputs corrected data obtained by correcting an error at the error position. | 12-04-2008 |
| 20100100702 | Arithmetic processing apparatus, TLB control method, and information processing apparatus - An arithmetic processing apparatus includes a main TLB that stores therein, as a page table, entries indicating correspondences between virtual and physical addresses, and a micro TLB that stores therein part of the table. The apparatus associates together the physical address stored in the main TLB, the virtual address associated with the physical address, and a context ID included in an address-translation request and registers these associated together in the micro TLB as an entry. When receiving the request, the apparatus does not translate the context ID included in the request into a context value but searches for an entry matching the virtual address and the context ID included in the request. When the entry is searched for and found, the response is the physical address included in the entry. When the entry is searched for and not found, the request is transmitted to the main TLB. | 04-22-2010 |
| 20100106936 | Calculator and TLB control method - A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro TLB that stores therein part of the page table stored in the main TLB. In the micro TLB, a TLB virtual address [63:13] and a TLB absolute address [46:13] are registered in a correlated manner. With such configuration, when registering an address translation pair in the micro TLB, the calculator chops the address translation pair to a page size of a first size or a fourth size to register it in the micro TLB. Upon receiving an address translation request, the calculator searches for an address corresponding to the page size of the first size or the fourth size registered in the micro TLB, so that address comparison conditions can be reduced, enabling to improve a processing performance. | 04-29-2010 |
| 20110083030 | CACHE MEMORY CONTROL DEVICE, CACHE MEMORY DEVICE, PROCESSOR, AND CONTROLLING METHOD FOR STORAGE DEVICE - A cache memory control device for controlling includes: a clock control unit that controls a clock supply unit among a plurality of clock supply units for supplying clocks to the plurality of cache memories to disable supplying of a clock to cache memories other than a first cache memory when an instruction control unit requests second data stored continuously with first data in the first cache memory. | 04-07-2011 |
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| 20080283840 | THIN FILM TRANSISTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND LIQUID CRYSTAL DISPLAY DEVICE - The present invention relates to a thin film transistor device formed on an insulating substrate of a liquid crystal display device and others, a method of manufacturing the same, and a liquid crystal display device. In structure, there are provided the steps of forming a negative photoresist film on a first insulating film for covering a first island-like semiconductor film, forming a resist mask that has an opening portion in an inner region with respect to a periphery of the first island-like semiconductor film by exposing/developing the negative photoresist film from a back surface side of a transparent substrate, etching the first insulating film in the opening portion of the resist mask, forming a second insulating film for covering the first insulating film and a conductive film thereon, and forming a first gate electrode and a second gate electrode by patterning the conductive film. | 11-20-2008 |
| 20090008644 | THIN FILM TRANSISTOR SUBSTRATE AND LIQUID CRYSTAL DISPLAY - A TFT substrate comprises a substrate, a gate electrode and a lower electrode of a capacitor formed thereon, a first insulating layer formed thereon, a channel layer above the gate electrode and a lower layer of an upper electrode of the capacitor, a channel protection layer formed on an intermediate part of said channel layer and a capacitor protection layer formed on a connection region of the lower layer, source/drain electrodes formed on said channel layer and an upper layer of the upper electrode of the capacitor formed on the lower layer and covering the capacitor protection layer, a second insulating layer covering them, a first connection hole exposing the source electrode and a second connection hole exposing a connection region of said upper layer, which are penetrating the second insulating layer, and a pixel electrode formed thereon. | 01-08-2009 |
| 20090141226 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - In a liquid crystal display device, liquid crystal molecules are oriented in a vertical direction to the first substrate and the second substrate by the first molecule orientation film and the second molecule orientation film, respectively, in a non-driving state. A structural pattern is formed so as to extend in a first direction parallel to a surface of the liquid crystal layer and so as to form, in a driving state, an electric field periodically changing in a second direction that is parallel to the liquid crystal layer and vertical to the first direction. The liquid crystal molecules substantially tilt in the first direction in the driving state. | 06-04-2009 |
| 20100066955 | SUBSTRATE FOR USE IN A LIQUID CRYSTAL DISPLAY AND LIQUID CRYSTAL DISPLAY USING THE SAME - The invention relates to a substrate for use in a liquid crystal display of a CF-on-TFT structure in which a color filter is formed on the side of an array substrate in which a switching element is formed, and has an object to provide a substrate for use in a liquid crystal display, which enables simplification of a manufacturing process typified by a photolithography process and has high reliability. The substrate for use in the liquid crystal display is constructed to include external connection terminals which include first terminal electrodes electrically connected to gate bus lines led out from a plurality of pixel regions arranged on a glass substrate in a matrix form, second terminal electrodes formed of forming material of a pixel electrode and directly on the glass substrate, and electrode coupling regions for electrically connecting the first and the second terminal electrodes, and which electrically connect an external circuit and the gate bus lines. | 03-18-2010 |
| 20110216274 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - In a liquid crystal display device, liquid crystal molecules are oriented in a vertical direction to the first substrate and the second substrate by the first molecule orientation film and the second molecule orientation film, respectively, in a non-driving state. A structural pattern is formed so as to extend in a first direction parallel to a surface of the liquid crystal layer and so as to form, in a driving state, an electric field periodically changing in a second direction that is parallel to the liquid crystal layer and vertical to the first direction. The liquid crystal molecules substantially tilt in the first direction in the driving state. | 09-08-2011 |
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| 20090282141 | Server managing apparatus and server managing method - A controlling unit obtains server information from a server group in a chassis to store the obtained server information in a server information DB, an editing unit reads the server information from the server information DB, and generates, based on the read server information, as screen display information, physical server information, and logical server information including information on use application and attribute information for a logical server, which are related to a physical location of each physical server, and a displaying unit displays screen display information on a screen simulating the physical location of the physical server. | 11-12-2009 |
| 20090300313 | MEMORY CLEARING APPARATUS FOR ZERO CLEARING - A memory clear apparatus includes a processor that issues a memory clear request including a zero clear target area on a memory area and a zero clear target size, and a memory clearing circuit that receives the memory clear request from the processor, performs zero clearing on the zero clear target area based on the memory clear request, and transmits a memory clear completion notification to the processor. | 12-03-2009 |
| 20090300613 | INPUT/OUTPUT EMULATION SYSTEM FOR VIRTUAL MACHINE - An I/O emulation system for a virtual machine includes a command interpretation portion including a programmable logic device that detects completion of a plurality of device operating instructions, which corresponds to a device operating request for the virtual machine, output from the guest device driver included, a device control portion that converts the plurality of device operating instructions, which is notified by a virtual machine monitor, into an I/O command and a host device driver that outputs a device operating instruction for the actual device in accordance with the I/O command. | 12-03-2009 |
| 20090327645 | SWITCH, INFORMATION PROCESSING APPARATUS, AND ADDRESS TRANSLATION METHOD - A switch connects and disconnects an input and output control device to and from an input and output device. The switch includes a storage unit that stores therein a translation table for use in translating a physical address used on a virtual machine that a guest operating system specifies as a direct memory access transfer destination to the input and output device, into a physical address used on a real machine; and an address translating unit that translates an address contained in a direct memory access request issued by the input and output device into a physical address used on the real machine by referring to the translation table. | 12-31-2009 |
| 20100332637 | VIRTUAL-MACHINE MANAGEMENT PROGRAM AND METHOD FOR MANAGING VIRTUAL MACHINES - A method for managing virtual machines, the method causing a management server having a database includes link relation information and connected to a plurality of physical servers, on which virtual machine hosts are installed, the method includes updating the link relation information in such a manner that a link between a virtual machine host and a first virtual machine guest is disconnected, when information regarding the first virtual machine guest cannot be acquired from the virtual machine host and updating the link relation information stored in such a manner that a link between a virtual machine host and a second virtual machine guest, when information regarding the second virtual machine guest is acquired from the virtual machine host. | 12-30-2010 |
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| 20090009223 | PLL CIRCUIT AND SEMICONDUCTOR INTEGRATED DEVICE - A charge pump circuit comprises two MOS transistors serially connected between a power supply voltage VDD and ground, a switch SW | 01-08-2009 |
| 20100061498 | DATA RECEIVING CIRCUIT - A receiving circuit includes a clock generation circuit that generates a clock signal, an integration filter that stores a signal potential of an input signal and generates a first storage potential in a period in which the clock signal indicates one logic, a first analog-to-digital circuit that converts the first storage potential into a first digital value, and a data determination circuit that determines a logic of the input signal on a basis of the first digital value. | 03-11-2010 |
| 20100117690 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first buffer circuit transmitting input signals, a second buffer circuit having a lower drive capability than the first buffer circuit and transmitting the input signals, and a control circuit detecting transitions of the input signals, and activating the first buffer circuit during a period when the input signals make the transitions. | 05-13-2010 |
| 20100141306 | PARALLEL-SERIAL CONVERSION CIRCUIT AND DATA RECEIVING SYSTEM - A parallel-serial conversion circuit includes: a plurality of data terminals each receiving a data signal; a selection circuit configured to select at least one of the data signals received through the plurality of data terminals; a first latch circuit configured to latch an output from the selection circuit based on a clock signal; a replica selection circuit configured to select one of a plurality of signals and output the selected signal; and a timing-signal generating circuit configured to generate a timing signal for controlling the selection circuit based on the output from the replica selection circuit, wherein the output from the replica selection circuit is latched based on the clock signal. | 06-10-2010 |
