Doering

Andreas Doering, Adliswil CH

Patent application number	Description	Published
20080270754	USING FIELD PROGRAMMABLE GATE ARRAY (FPGA) TECHNOLOGY WITH A MICROPROCESSOR FOR RECONFIGURABLE, INSTRUCTION LEVEL HARDWARE ACCELERATION - A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.	10-30-2008

Patent application number	Description	Published
20080291913	Detecting a timeout of elements in an element processing system - Provides methods, systems and apparatus for timer management of an element processing system wherein timer intervals related to elements to be processed can be handled in a time-efficient manner. An example method is a method for detecting a timeout of elements in an element processing system wherein a timer value, indicating a timeout interval with respect to a given time base, is assigned to each of the elements when processed. From a number of elements processed, the timer value indicating a minimum timeout interval to expire is determined out of the number of timer values assigned to the number of elements being processed.	11-27-2008

Patent applications by Andreas Ch. Doering, Adliswil CH