| Patent application number | Description | Published |
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| 20090077145 | Reconfigurable arithmetic unit - A reconfigurable arithmetic circuit including a matrix having a plurality of partial product mask cells arranged in rows and columns, where rows and columns have incrementing arithmetic weights assigned, each partial product mask cell including a gate implementing a logical AND function of its inputs to provide an output, and a programmable memory cell connected to furnish input to the gate, a plurality of horizontally oriented conductors each connected to furnish input to the gates of the partial product mask cells of a row, and a plurality of diagonally oriented conductors each connected to furnish input to the gates of the partial product mask cells along the diagonal of increasing arithmetic weight of rows and columns, and a compression circuit receiving inputs from the gates of the partial product mask cells of the matrix, and furnishing outputs providing conventional arithmetic compression of its inputs in carry-saved format. | 03-19-2009 |
| 20090077153 | Reconfigurable arithmetic unit - A reconfigurable arithmetic circuit including a plurality of logical AND gates arranged in logical columns and rows, a plurality of conductors each connected to furnish input to the AND gates of a row, an array of memory cells each connected to furnish input to one of the AND gates, and a plurality of reconfigurable counting circuits, each counting circuit connected to receive the output of each of the AND gates in a column, each counting circuit being configurable to provide a count of parity of the outputs furnished by the AND gates of the column. | 03-19-2009 |
| Patent application number | Description | Published |
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| 20090022500 | METHOD AND SYSTEM FOR OPTOELECTRONICS TRANSCEIVERS INTEGRATED ON A CMOS CHIP - Methods and systems for optoelectronics transceivers integrated on a CMOS chip are disclosed and may include receiving optical signals from optical fibers via grating couplers on a top surface of a CMOS chip, which may include a guard ring. Photodetectors may be integrated in the CMOS chip. A CW optical signal may be received from a laser source via grating couplers, and may be modulated using optical modulators, which may be Mach-Zehnder and/or ring modulators. Circuitry in the CMOS chip may drive the optical modulators. The modulated optical signal may be communicated out of the top surface of the CMOS chip into optical fibers via grating couplers. The received optical signals may be communicated between devices via waveguides. The photodetectors may include germanium waveguide photodiodes, avalanche photodiodes, and/or heterojunction diodes. The CW optical signal may be generated using an edge-emitting and/or a vertical-cavity surface emitting semiconductor laser. | 01-22-2009 |
| 20100006784 | METHOD AND SYSTEM FOR A LIGHT SOURCE ASSEMBLY SUPPORTING DIRECT COUPLING TO AN INTEGRATED CIRCUIT - Methods and systems for a light source assembly supporting direct coupling to a photonically enabled complementary metal-oxide semiconductor (CMOS) chip are disclosed. The assembly may include a laser, a microlens, a turning mirror, reciprocal and/or non-reciprocal polarization rotators, and an optical bench. The laser may generate an optical signal that may be focused utilizing the microlens. The optical signal may be reflected at an angle defined by the turning mirror, and may be transmitted out of the light source assembly to one or more grating couplers in the chip. The laser may include a feedback insensitive laser. The light source assembly may include two electro-thermal interfaces between the optical bench, the laser, and a lid affixed to the optical bench. The turning mirror may be integrated in a lid affixed to the optical bench or may be integrated in the optical bench. | 01-14-2010 |
| 20100008675 | INTEGRATED TRANSCEIVER WITH LIGHTPIPE COUPLER - Systems and methods for configuring an integrated transceiver are disclosed. In one embodiment, very small form factor transceivers can be configured to allow 10 G optical interconnects over distances up to 2 km. Transceiver circuitry can be integrated on a single die, and be electrically connected to a transmitter such as a laser-diode and a receiver such as a photo-diode. In one embodiment, the laser and photo diodes can be edge-operating, and be mounted on the die. In one embodiment, one or both of the diodes can be surface-operating so as to allow relaxation of alignment requirement. In one embodiment, one or both of the diodes can be mounted on a submount that is separate from the die so as to facilitate separate assembly and testing. In one embodiment, the diodes can be optically coupled to a ferrule via an optical coupling element so as to manage loss in certain situations. | 01-14-2010 |
| 20100046955 | INTEGRATED TRANSCEIVER WITH LIGHTPIPE COUPLER - Systems and methods for configuring an integrated transceiver are disclosed. In one embodiment, very small form factor transceivers can be configured to allow 10G optical interconnects over distances up to 2k km. Transceiver circuitry can be integrated on a single die, and be electrically connected to a transmitter such as a laser-diode and a receiver such as a photo-diode. In one embodiment, the laser and photo diodes can be edge-operating, and be mounted on the die. In one embodiment, one or both of the diodes can be surface-operating so as to allow relaxation of alignment requirement. In one embodiment, one or both of the diodes can be mounted to a submount that is separate from the die so as to facilitate separate assembly and testing. In one embodiment, the diodes can be optically coupled to a ferrule via an optical coupling element so as to manage loss in certain situations. | 02-25-2010 |
| 20100059822 | METHOD AND SYSTEM FOR MONOLITHIC INTEGRATION OF PHOTONICS AND ELECTRONICS IN CMOS PROCESSES - Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer. | 03-11-2010 |
| 20100209114 | Method and System for Single Laser Bidirectional Links - A method and system for single laser bidirectional links are disclosed and may include communicating a high speed optical signal from a transmit CMOS photonics chip to a receive CMOS photonics chip and communicating a low-speed optical signal from the receive CMOS photonics chip to the transmit CMOS photonics chip via one or more optical fibers. The optical signals may be coupled to and from the CMOS photonics chips utilizing single-polarization grating couplers. The optical signals may be coupled to and from the CMOS photonics chips utilizing polarization-splitting grating couplers. The optical signals may be amplitude or phase modulated. The optical fibers may comprise single-mode or polarization-maintaining fibers. A polarization of the high-speed optical signal may be configured before communicating it over the single-mode fibers. The low-speed optical signal may be generated by modulating the received high-speed optical signal or from a portion of the received high-speed optical signal. | 08-19-2010 |
