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Dixon, TX
Christopher J. Dixon, Corpus Christi, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110247786 | Heat exchanger maintenance technique - A heat exchanger is cleaned, inspected and/or plugged while the heat exchange is in operation. In some embodiments, the heat exchanger comprises a channel cover having valve-seal assemblies allowing isolation tools to be inserted through the channel cover into sealing engagement with the ends of tubes to provide a flow path separate from the normal flow paths through the heat exchanger. Cleaning and/or inspecting can be done through the isolation tools and tubes that are leaking can be plugged through the valve-seal assemblies. In some embodiments, brushes are located inside the heat exchanger and can be independently advanced into cleaning relation with a large majority of the tubes. | 10-13-2011 |
Hong Dixon, Helotes, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080299066 | ENERGY-ACTIVATED COMPOSITIONS FOR CONTROLLED SUSTAINED RELEASE OF A GAS - A composition for energy-controlled generation and release of at least one gas, which includes an energy-activated catalyst capable of being activated by electromagnetic energy, and a solid or a liquid containing anions capable of being oxidized by the activated catalyst or reacted with species generated during activation of the catalyst to generate at least one gas. The composition, when exposed to electromagnetic energy, is capable of generating and releasing the gas after activation of the catalyst and oxidation or reaction of the anions. | 12-04-2008 |
| 20100040692 | TWO PHASE BIOACTIVE FORMULATIONS - The present invention relates to two-phase systems of a bioactive ingredient in particle form that has limited or no solubility in a liquid medium, which provides stability to the active ingredient that is similar to the active ingredient when in the solid state. The active ingredient may be capable of therapeutically treating for the presence of a cholinesterase inhibitor. | 02-18-2010 |
| 20100086601 | Modified Calcium Phosphate Nanoparticle Formation - The present disclosure relates to non-aggregating nanoparticles and their associated methods of preparation. The nanoparticles may have a surface and a size range of 1 nm to 999 nm, along with a zeta potential of −50 to 50 millivolts. A polycation and/or polyanion may be disposed on the nanoparticle surface. In addition, an active ingredient may be encapsulated within the nanoparticles or associated with the polycation or polyanion on the nanoparticle surface. | 04-08-2010 |
| 20100098754 | PROCESSING OF HEAT-SENSITIVE ACTIVE AGENTS - The present disclosure relates to a method of melt processing an active agent. The method may include encapsulating an active agent in a first polymer material exhibiting a first processing temperature T | 04-22-2010 |
| 20110195125 | Nanoparticles For Drug Delivery To The Central Nervous System - The present disclosure relates to compositions and methods for producing nanoparticles to provide relatively more rapid delivery of such particles across the blood-brain barrier. The nanoparticles may be formed from bis-quaternary pyridinium-aldoxime salts that may also be of a specific polymorphic structure and which may be formed in either hydrophobic or hydrophilic type liquid media. In addition, the nanoparticle for transport across the blood-brain barrier may comprise a polymeric resin encapsulating a bis-quaternary pyridinium-2-aldoxime salt of the formula: | 08-11-2011 |
Richard A. F. Dixon, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090004268 | Methods and Compositions for Treatment of an Interstitial Lung Disease - Provided herein are methods of treatment of an interstitial lung disease (ILD) by administering an endothelin antagonist, such as sitaxsentan or a pharmaceutically acceptable salt thereof. | 01-01-2009 |
Robert C. Dixon, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090024346 | IMPORTATION OF VIRTUAL SIGNALS INTO ELECTRONIC TEST EQUIPMENT TO FACILITATE TESTING OF AN ELECTRONIC COMPONENT - Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component. The method includes: storing simulation data resulting from simulation testing of an electronic component's design; employing electronic test equipment to perform real-time testing of the actual electronic component and obtain real-time test signals therefor; automatically correlating the stored simulation data with the actual real-time test signals; and performing at least one of overlaying and/or displaying the correlated simulation data as virtual signals with the real-time test signals; and employing a trigger event automatically ascertained from the stored simulation data and triggering the electronic test equipment based thereon, thereby automatically controlling real-time testing of the electronic component via the stored simulation data. | 01-22-2009 |
| 20090295449 | DUTY CYCLE MEASUREMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE - A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance. | 12-03-2009 |
| 20100100786 | SERIAL TEST MODE OF AN INTEGRATED CIRCUIT (IC) - A methodology to perform testing of integrated circuits (IC) wherein a reduced number of Input/Output (IO) pins may used to load testing patterns and capture test results from test structures after an IC has been installed in its intended application is provided. This methodology utilizes a software engine that receives and translates a parallel test pattern into serial data patterns operable to be provided on the reduced number of I/O pins. A serial process loader then loads the serial data patterns to the test structures within the IC. The IC receives the serial patterns and in turn translates them into parallel test patterns in order to apply the test patterns to the appropriate test structures. The results are captured and then translated into a serial format for communication from the IC to a test unit for analysis. | 04-22-2010 |
Robert Christopher Dixon, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090094496 | System and Method for Improved LBIST Power and Run Time - A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets. | 04-09-2009 |
| 20090210566 | MULTI-CHIP DIGITAL SYSTEM SIGNAL IDENTIFICATION APPARATUS - The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers. | 08-20-2009 |