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Ditlow
Gary Ditlow, New York, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100106996 | SerDes double rate bitline with interlock to block precharge capture - An embodiment of the invention provides a method of separating an early clock pulse and a late clock pulse into two different latches, wherein the early clock pulse is generated through a bit line. In response to the early clock pulse rising, a first data waveform is sent to a fourth data waveform. In response to a third data waveform rising, an early precharge is turned off. In response to the turning off of the early precharge and in response to a fifth data waveform dropping, an eighth data waveform rises if the first data waveform has a value of 1. In response to a sixth data waveform rising, a first pulse latch is opened | 04-29-2010 |
Gary S. Ditlow, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110051482 | CONTENT ADDRESSABLE MEMORY ARRAY PROGRAMMED TO PERFORM LOGIC OPERATIONS - A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed. | 03-03-2011 |
| 20110051485 | CONTENT ADDRESSABLE MEMORY ARRAY WRITING - A memory system for storing one or more addresses includes a transposable memory having word lines, bit lines, transposed word lines and transposed bit lines and that receives and stores an input array having dimensions M by N and a content addressable memory (CAM) that reads the transposed word lines of the transposable memory to form input words and that stores the input words in an N by M array. | 03-03-2011 |
| 20110051486 | CONTENT ADDRESSABLE MEMORY REFERENCE CLOCK - A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic. | 03-03-2011 |
| 20110134676 | RESISTIVE MEMORY DEVICES HAVING A NOT-AND (NAND) STRUCTURE - Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element. | 06-09-2011 |
Gary S. Ditlow, Yorktown, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110051483 | CONTENT ADDRESSABLE MEMORY ARRAY - A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of a logical combination of at least two different inputs. | 03-03-2011 |
Gary S. Ditlow, Garrison, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090251171 | Methods and Apparatus for Monitoring Power Gating Circuitry and for Controlling Circuit Operations in Dependence on Monitored Power Gating Conditions - A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage. | 10-08-2009 |
| 20100266081 | System and Method for Double Rate Clocking Pulse Generation With Mistrack Cancellation - A method for generating a dual rate clock circuit the method including coupling the output terminal of a first local clock buffer to the input of a second local clock buffer through at least one inverter circuit and driving the first local clock buffer with a base signal. The method also includes generating an early clock signal with the first local clock buffer based on the base signal and generating a delayed early clock signal by delaying the first local clock signal with the at least one inverter. The method also includes generating a later clock signal by driving the second local clock buffer with the delayed early clock signal wherein the second local clock buffer and the late clock signal generated by the second local clock buffer are synchronized and correlated with the first local clock buffer and the early clock signal generated by the first local clock buffer. | 10-21-2010 |