| Patent application number | Description | Published |
|---|
| 20080228460 | METHOD FOR DETERMINING BEST AND WORST CASES FOR INTERCONNECTS IN TIMING ANALYSIS - Roughly described, signal propagation delay values are estimated for a plurality of interconnects in a circuit design. For each interconnect, the propagation delay value(s) are estimated in dependence upon a preliminary approximate determination of whether the signal propagation delay is dominated more by an interconnect capacitance term or by an interconnect capacitance and resistance product term. If it is dominated more by the interconnect capacitance term, then the parameter values used for a minimum propagation delay calculation are obtained assuming a smallest capacitance process variation case and the parameter values used for a maximum propagation delay calculation are obtained assuming a largest capacitance process variation case. If the signal propagation delay is dominated more by the interconnect capacitance and resistance product term, then the opposite assumptions are made. Preferably the approximate determination is made by comparing Rint to k*Rd. | 09-18-2008 |
| 20080296698 | METHOD FOR SUPPRESSING LAYOUT SENSITIVITY OF THRESHOLD VOLTAGE IN A TRANSISTOR ARRAY - A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout | 12-04-2008 |
| 20080297237 | METHOD FOR COMPENSATION OF PROCESS-INDUCED PERFORMANCE VARIATION IN A MOSFET INTEGRATED CIRCUIT - An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing. | 12-04-2008 |
| 20080301599 | METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY - An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations. | 12-04-2008 |
| 20090007043 | Managing Integrated Circuit Stress Using Dummy Diffusion Regions - Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors. | 01-01-2009 |
| 20090108293 | Method for Suppressing Lattice Defects in a Semiconductor Substrate - A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer. | 04-30-2009 |
| 20090108408 | Method for Trapping Implant Damage in a Semiconductor Substrate - A method for minimizing the effects of defects produced in a implantated area of a crystal lattice during dopant implantation in the lattice. The method begins with the step of implanting a trap layer of trap atoms, the trap atoms having a size less than that of the lattice member atoms. After implantation, the lattice is annealed for a time sufficient for interstitial defect atoms to be emitted from the defect area. In that manner, energetically stable pairs are formed between trap atoms and emitted interstitial atoms. | 04-30-2009 |
| 20090113368 | FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM - A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell. | 04-30-2009 |
| 20090217217 | METHOD OF CORRELATING SILICON STRESS TO DEVICE INSTANCE PARAMETERS FOR CIRCUIT SIMULATION - Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same as the first model, with its stress sensitivity disabled. Thereafter, a substitute stress analyzer can be used to determine a stress-adjusted value for the first performance measure, and the mathematical relationship can be used to convert that value into specific values for the one or more instance parameters. These values are then provided to the second transistor model for use in simulating the characteristics of the particular transistor during circuit simulation. | 08-27-2009 |
| 20090236673 | METHOD FOR SUPPRESSING LAYOUT SENSITIVITY OF THRESHOLD VOLTAGE IN A TRANSISTOR ARRAY - A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout | 09-24-2009 |
| 20090288048 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 11-19-2009 |
| 20090288049 | Method for Rapid Estimation of Layout-Dependent Threshold Voltage Variation in a MOSFET Array - An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations. | 11-19-2009 |
| 20090307649 | SYSTEM AND METHOD FOR MODIFYING A DATA SET OF A PHOTOMASK - The present invention provides a method for compensating, infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer. | 12-10-2009 |
| 20090313595 | STRESS-MANAGED REVISION OF INTEGRATED CIRCUIT LAYOUTS - Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors. | 12-17-2009 |
| 20100019317 | Managing Integrated Circuit Stress Using Stress Adjustment Trenches - Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors. | 01-28-2010 |
| 20100023899 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
| 20100023900 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
| 20100023901 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
| 20100023902 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
| 20100024978 | STRESS ENGINEERING FOR CAP LAYER INDUCED STRESS - Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as practical from the N-channel diffusion, toward the P-channel diffusion. In another aspect, roughly described, a gate conductor crosses a P-channel diffusion region and terminates as far as practical beyond the edge without making undesirable electrical contact with any other features of the integrated circuit design, and without overlying any other diffusion regions. A compressively strained cap layer overlies the P-channel diffusion. In yet another aspect, roughly described, a gate conductor crosses an N-channel diffusion and extends by as short a distance as practical before terminating or turning. A tensile strained cap material overlies the N-channel diffusion. | 02-04-2010 |
| 20100025777 | METHOD FOR SUPPRESSING LATTICE DEFECTS IN A SEMICONDUCTOR SUBSTRATE - A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer. | 02-04-2010 |
| 20100029050 | STRESS ENGINEERING FOR CAP LAYER INDUCED STRESS - Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as practical from the N-channel diffusion, toward the P-channel diffusion. In another aspect, roughly described, a gate conductor crosses a P-channel diffusion region and terminates as far as practical beyond the edge without making undesirable electrical contact with any other features of the integrated circuit design, and without overlying any other diffusion regions. A compressively strained cap layer overlies the P-channel diffusion. In yet another aspect, roughly described, a gate conductor crosses an N-channel diffusion and extends by as short a distance as practical before terminating or turning. A tensile strained cap material overlies the N-channel diffusion. | 02-04-2010 |
| 20100042958 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 02-18-2010 |
| 20110078639 | FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM - A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell. | 03-31-2011 |
