| Patent application number | Description | Published |
|---|
| 20080203549 | STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE INTERCONNECT INTERFACE - A stackable integrated circuit package system includes: forming a first integrated circuit die having a small interconnect and a large interconnect provided thereon; forming an external interconnect, having an upper tip and a lower tip, from a lead frame; mounting the first integrated circuit die on the external interconnect with the small interconnect on the lower tip and below the upper tip; and encapsulating around the small interconnect and around the large interconnect with an exposed surface. | 08-28-2008 |
| 20080315411 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING - An integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system. | 12-25-2008 |
| 20090140441 | Wafer Level Die Integration and Method - In a wafer level chip scale package (WLSCP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die is disposed over the second semiconductor die. The second and third semiconductor die are attached with an adhesive. A second RDL electrically connects the first, second, and third semiconductor die. The second RDL can be a bond wire. Passivation layers isolate the RDLs and second and third semiconductor die. A plurality of solder bumps is formed on a surface of the WLSCP. The solder bumps are formed on under bump metallization which electrically connects to the RDLs. The solder bumps electrically connect to the first, second, or third semiconductor die through the first and second RDLs. | 06-04-2009 |
| 20090152700 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTABLE INTEGRATED CIRCUIT DIE - A mountable integrated circuit package system includes: mounting an integrated circuit die over a package carrier; connecting a first internal interconnect between the integrated circuit die and the package carrier; and forming a package encapsulation over the package carrier and the first internal interconnect, with the integrated circuit die partially exposed within a recess of the package encapsulation. | 06-18-2009 |
| 20090152701 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE INTEGRATION - An integrated circuit package system comprising: providing a package substrate; attaching a base package having a portion of the base package substantially exposed over the package substrate; forming a cavity through the package substrate to the base package; and attaching a device partially in the cavity and connected to the portion of the base package substantially exposed. | 06-18-2009 |
| 20090152706 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECT LOCK - An integrated circuit package system includes: mounting a device structure over a package carrier; connecting an internal interconnect between the device structure and the package carrier; forming an interconnect lock over the internal interconnect over the device structure with interconnect lock exposing the device structure; and forming a package encapsulation adjacent to the interconnect lock and over the package carrier. | 06-18-2009 |
| 20090166825 | System and Apparatus for Wafer Level Integration of Components - In a semiconductor package, a substrate has an active surface containing a plurality of active circuits. An adhesive layer is formed over the active surface of the substrate, and a known good unit (KGU) is mounted to the adhesive layer. An interconnect structure electrically connects the KGU and active circuits on the substrate. The interconnect structure includes a wire bond between a contact pad on the substrate and a contact pad on the KGU, a redistribution layer on a back surface of the substrate, opposite the active surface, a through hole via (THV) through the substrate that electrically connects the redistribution layer and wire bond, and solder bumps formed in electrical contact with the redistribution layer. The KGU includes a KGU substrate for supporting the KGU, a semiconductor die disposed over the KGU substrate, and an encapsulant formed over the semiconductor die. | 07-02-2009 |
| 20090179312 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM - An integrated circuit package-on-package stacking method includes forming a leadframe interposer including: forming a leadframe having a lead; forming a molded base only supporting the lead; and singulating the leadframe interposer from the leadframe. | 07-16-2009 |
| 20090289356 | Wirebondless Wafer Level Package with Plated Bumps and Interconnects - A semiconductor package includes a carrier strip having a die cavity and a plurality of bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip using a die attach adhesive. In one embodiment, a top surface of the semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. Underfill material is deposited into the die cavity between the semiconductor die and a surface of the die cavity. In one embodiment, a passivation layer is deposited over the semiconductor die, and a portion of the passivation layer is etched to expose a contact pad of the semiconductor die. A metal layer is deposited over the package. The metal layer forms a package bump and a plated interconnect between the package bump and the contact pad of the semiconductor die. Encapsulant is deposited over the semiconductor package. | 11-26-2009 |
| 20100025833 | RDL PATTERNING WITH PACKAGE ON PACKAGE SYSTEM - An integrated circuit package system includes: providing an internal device; encapsulating the internal device with an encapsulation having an outer surface; and forming a redistribution line having connection points on the outer surface of the encapsulation. | 02-04-2010 |
| 20100072586 | QUAD FLAT PACK IN QUAD FLAT PACK INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes: providing a base package having a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation; mounting an outer lead on the periphery of the base package; mounting a second integrated circuit above the base package and connected to the outer lead with the interconnects; and partially encapsulating, the base package and the outer leads with an outer encapsulation leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed. | 03-25-2010 |
| 20100072589 | SEMICONDUCTOR PACKAGE SYSTEM WITH DIE SUPPORT PAD - A semiconductor package system includes: providing a leadframe with a lead; making a die support pad separately from the leadframe; attaching a semiconductor die to the die support pad through a die attach adhesive, the semiconductor die being spaced from the lead; and connecting a bonding pad on the semiconductor die to the lead using a bonding wire. | 03-25-2010 |
| 20100072599 | Semiconductor Device and Method of Forming a Wafer Level Package with Top and Bottom Solder Bump Interconnection - A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps. | 03-25-2010 |
| 20100176497 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM - An integrated circuit package-on-package stacking system includes a leadframe interposer including: a leadframe having a lead; a molded base on a portion of the lead for only supporting the lead; and the leadframe interposer singulated from the leadframe, wherein the lead is bent to support a stack-up height. | 07-15-2010 |
| 20100219523 | STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM - A stackable integrated circuit package system includes: a substrate having a first side and a second side opposite the first side, the substrate having a cavity provided therein; a first integrated circuit die in the cavity with a first interconnect extending out from the cavity without connection and a second interconnect connected to the first side; a first mold compound to cover the first integrated circuit die, the second interconnect, and a portion of the first interconnect; a second integrated circuit die mounted to the first integrated circuit die with a third interconnect connected to the second side; a second mold compound to cover the second integrated circuit die and the third interconnect; and external interconnects, not encapsulated by the second encapsulant, mounted on the second side. | 09-02-2010 |
| 20100237477 | Semiconductor Device and Method of Mounting Pre-Fabricated Shielding Frame over Semiconductor Die - A semiconductor device includes a pre-fabricated shielding frame mounted over a sacrificial substrate and semiconductor die. An encapsulant is deposited through an opening in the shielding frame around the semiconductor die. A first portion of the shielding frame to expose the encapsulant. Removing the first portion also leaves a second portion of the shielding frame over the semiconductor die as shielding from interference. A third portion of the shielding frame around the semiconductor die provides a conductive pillar. A first interconnect structure is formed over a first side of the encapsulant, shielding frame, and semiconductor die. The sacrificial substrate is removed. A second interconnect structure over the semiconductor die and a second side of the encapsulant. The shielding frame can be connected to low-impedance ground point through the interconnect structures or TSV in the semiconductor die to isolate the die from EMI and RFI, and other inter-device interference. | 09-23-2010 |
| 20100264528 | QUAD FLAT PACK IN QUAD FLAT PACK INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a base package having a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation; mounting an outer lead on the periphery of the base package; mounting a second integrated circuit above the base package and connected to the outer lead with the interconnects; and partially encapsulating, the base package and the outer leads with an outer encapsulation leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed. | 10-21-2010 |
| 20100314780 | Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers - A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die. | 12-16-2010 |
| 20100320588 | Semiconductor Device and Method of Forming Prefabricated Heat Spreader Frame with Embedded Semiconductor Die - A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated. | 12-23-2010 |
| 20110012270 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system. | 01-20-2011 |
| 20110024888 | Semiconductor Device and Method of Mounting Die with TSV in Cavity of Substrate for Electrical Interconnect of FI-POP - A semiconductor device has a substrate with a cavity formed through first and second surfaces of the substrate. A conductive TSV is formed through a first semiconductor die, which is mounted in the cavity. The first semiconductor die may extend above the cavity. An encapsulant is deposited over the substrate and a first surface of the first semiconductor die. A portion of the encapsulant is removed from the first surface of the first semiconductor die to expose the conductive TSV. A second semiconductor die is mounted to the first surface of the first semiconductor die. The second semiconductor die is electrically connected to the conductive TSV. An interposer is disposed between the first semiconductor die and second semiconductor die. A third semiconductor die is mounted over a second surface of the first semiconductor die. A heat sink is formed over a surface of the third semiconductor die. | 02-03-2011 |
| 20110079899 | EMBEDDED INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an embedded integrated circuit package system includes: forming a first conductive pattern on a first structure; connecting a first integrated circuit die, having bumps on a first active side, directly on the first conductive pattern by the bumps; forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern; forming a channel in the substrate forming encapsulation; and applying a conductive material in the channel. | 04-07-2011 |
| 20110129965 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE SYSTEM WITH DIE SUPPORT PAD - A method for manufacturing a semiconductor package system includes: providing a leadframe, having an open center, with leads adjacent to a peripheral edge of the leadframe; making a die support pad, formed without tie bars, separately from the leadframe; providing a coverlay tape for positioning the support pad centered within the leadframe; attaching a semiconductor die to the die support pad through a die attach adhesive, the semiconductor die being spaced from the leads; and connecting a bonding pad on the semiconductor die to one of the leads using a bonding wire. | 06-02-2011 |
| 20110140247 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELDED PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate assembly having a connection path; mounting a base device over the substrate assembly with a mount layer; mounting a stack device over the base device and having a stack die and a stack-organic-material; forming a stack-through-via in the stack-organic-material of the stack device and connected to the stack die and the substrate assembly; and applying a shield layer directly on a planarized surface of the stack-through-via partially exposed from the stack-organic-material. | 06-16-2011 |
| 20110140251 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REMOVABLE BACKING ELEMENT HAVING PLATED TERMINAL LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes providing a first frame having a first removable backing element connecting a first die attach pad and a first plurality of terminal leads. A first die is attached to the first die attach pad. A substrate is provided. A second die is attached to the substrate. The first die is attached to the second die with a plurality of die interconnects. The first removable backing element is removed after connecting the first die to the second die. | 06-16-2011 |
| 20110147899 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING - A method of manufacturing an integrated circuit packaging system includes: providing an inner lead and an outer lead, the inner lead having an inner peripheral side with a non-linear contour; forming a bump contact, having a groove in and a mesa from the inner lead or the outer lead, the groove adjacent to the mesa; mounting a first device adjacent to the inner lead; connecting a second device to the mesa; and forming an encapsulation material over the first device, the inner lead, and the outer lead and covering the second device. | 06-23-2011 |
