Patent application number | Description | Published |
20080242079 | IN-SITU FORMATION OF CONDUCTIVE FILLING MATERIAL IN THROUGH-SILICON VIA - The formation of electronic assemblies including a die having through vias is described. In one embodiment, a method includes providing Si die including a first surface and a second surface opposite the first surface, and forming a via extending through the Si die from the first surface to the second surface. The via is formed to have a larger width at the first surface than at the second surface, the larger width at the first surface being no less than 100 microns. The method also includes placing a plurality of particles in the via, wherein at least some of the particles comprise a polymer and at least some of the particles comprise a metal. The method also includes heating the die and the particles in the via to cross-link at least part of the polymer in the via, and cooling the die to solidify the polymer and form a electrically conductive composite including the cross-linked polymer and the metal in the via. Other embodiments are described and claimed. | 10-02-2008 |
20090004317 | HIGH THERMAL CONDUCTIVITY MOLDING COMPOUND FOR FLIP-CHIP PACKAGES - A molding compound for use in an integrated circuit package comprises an epoxy and a thermally conductive filler material. The thermally conductive filler material comprises between 70% and 95% of the molding compound and has a thermal conductivity between 10 W/m-K and 3000 W/m-K. | 01-01-2009 |
20090321922 | SELF-HEALING THERMAL INTERFACE MATERIALS FOR SEMICONDUCTOR PACKAGES - A semiconductor package is described. The semiconductor package includes an internal housing and a semiconductor die coupled with the internal housing by a layer of self-healing thermal interface material. | 12-31-2009 |
20100264536 | SELF-HEALING THERMAL INTERFACE MATERIALS FOR SEMICONDUCTOR PACKAGES - A semiconductor package is described. The semiconductor package includes an internal housing and a semiconductor die coupled with the internal housing by a layer of self-healing thermal interface material. | 10-21-2010 |
20110151624 | Coating for a microelectronic device, treatment comprising same, and method of managing a thermal profile of a microelectronic die - A coating for a microelectronic device comprises a polymer film ( | 06-23-2011 |
20110159256 | Treatment for a microelectronic device and method of resisting damage to a microelectronic device using same - A treatment for a microelectronic device comprises a dicing tape ( | 06-30-2011 |
20120074597 | FLEXIBLE UNDERFILL COMPOSITIONS FOR ENHANCED RELIABILITY - Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed. | 03-29-2012 |
20120153494 | FORMING DIE BACKSIDE COATING STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a patterned die backside film (DBF) on a backside of a die, wherein the patterned DBF comprises an opening surrounding at least one through silicon via (TSV) pad disposed on the backside of the die. | 06-21-2012 |
20130017650 | COATING FOR A MICROELECTRONIC DEVICE, TREATMENT COMPRISING SAME,AND METHOD OF MANAGING A THERMAL PROFILE OF A MICROELECTRONIC DIE - A coating for a microelectronic device comprises a polymer film ( | 01-17-2013 |
20140167217 | PACKAGE WITH DIELECTRIC OR ANISOTROPIC CONDUCTIVE (ACF) BUILDUP LAYER - Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to an integrated circuit substrate by an interface layer. In one embodiment, the interface layer may include an anisotropic portion configured to conduct electrical signals in the out-of-plane direction between one or more components, such as a die and an integrated circuit substrate. In another embodiment, the interface layer may be a dielectric or electrically insulating layer. In yet another embodiment, the interface layer may include an anisotropic portion that serves as an interconnect between two components, a dielectric or insulating portion, and one or more interconnect structures that are surrounded by the dielectric or insulating portion and serve as interconnects between the same or other components. Other embodiments may be described and/or claimed. | 06-19-2014 |
20140175657 | METHODS TO IMPROVE LASER MARK CONTRAST ON DIE BACKSIDE FILM IN EMBEDDED DIE PACKAGES - Apparatus including a die including a device side with contact points; and a build-up carrier disposed on the device side of the die; and a film disposed on the back side of the die, the film including a markable material including a mark contrast of at least 20 percent. Method including forming a body of a build-up carrier adjacent a device side of a die; and forming a film on a back side of the die, the film including a markable material including a mark contrast of at least 20 percent. Apparatus including a package including a microprocessor disposed in a carrier; a film on the back side of the microprocessor, the film including a markable material including a mark contrast of at least 20 percent; and a printed circuit board coupled to at least a portion of the plurality of conductive posts of the carrier. | 06-26-2014 |