Patent application number | Description | Published |
20080274087 | BRAIN TISSUE DAMAGE THERAPIES - A cultured pluripotent animal cell that is CD13+, CD90+, and CD117−. Also disclosed are methods for making the cell and methods of treating a brain tissue damage and increasing the expression level of a neuraltrophic factor in a subject. | 11-06-2008 |
20120270314 | NON-TUMORIGENIC EXPANSION OF PLURIPOTENT STEM CELLS - A method for expansion of human embryonic stem (hES) cells in a medium including human umbilical cord-derived mesenchymal stem cells (HUCMSCs) as a feeder is provided. The human embryonic stem cells (hES) maintain the features of embryonic stem cells in the medium, such as pluripotency, unlimited undifferentiated proliferation and normal karyotypes. Also provided is a method for non-tumorigenic expansion of the human embryonic stem cells (hES) that is free from forming teratoma. | 10-25-2012 |
20130059373 | ENDOMETRIAL POLYP STEM CELL - An endometrial polyp stem cell is disclosed in the present invention. The endometrial polyp stem cell is isolated from an endometrial polyp tissue, expresses vimentin, CD13, CD29, CD44, and CD90, and has no expression of CD1q, CD3, CD34, and CD45. | 03-07-2013 |
Patent application number | Description | Published |
20090323013 | MODULIZED DISPLAY COMPONENT AND MANUFACTURING METHOD THEREOF - A modulized display component and a manufacturing method for the same are disclosed in this invention. The display component of this invention is designed according to a modulization concept so that it can be attached to any driving circuit layer. Further, various manufacturing techniques can be used to form the alignment layers and protective layers in order to fabricate a trans-reflective, reflective, or transmissive color displaying component. | 12-31-2009 |
20110056534 | SEMITRANSPARENT PHOTOVOLTAIC FILM - A semitransparent photovoltaic film is provided, including a flexible substrate that integrates a plurality of first and second planar portions, and a plurality of photovoltaic cells. An angle is also included correspondingly between the first and the second planar portions. The photovoltaic cells are formed on a plurality of surfaces of the first planar portions of the flexible substrate. According to a design of the semitransparent photovoltaic film, most directly incident sunlight is absorbed and then converted into electricity, and most of the lights progressing horizontally or on a upward slant can pass through the film, thereby achieving the transparent visual effect. | 03-10-2011 |
20120152355 | ORGANIC SOLAR CELL - An organic solar cell is provided. The organic solar cell includes a substrate, a first electrode, a second electrode and a photoelectric conversion layer. The first electrode is disposed on the substrate. The second electrode is disposed on the first electrode. The photoelectric conversion layer is disposed between the first electrode and the second electrode. The photoelectric conversion layer contains a fully conjugated block copolymer including a block having an electron withdrawing group and a block having an electron donating group. | 06-21-2012 |
Patent application number | Description | Published |
20130257462 | PACKAGE STRUCTURE WITH CONFORMAL SHIELDING AND INSPECTION METHOD USING THE SAME - A package structure with conformal shielding includes a substrate providing electrically connected inner grounding structures, a chip module mounted on the substrate, a molding compound covering the chip module and one surface of the substrate, and a conductive shielding layer covering the molding compound and the lateral sides of the substrate, and electrically connected with a part of the inner grounding structures. The substrate further provides one or multiple independent conductive structures electrically connected with the conductive shielding layer and exposed to the outside. By measuring the resistance value between one independent conductive structure and the conductive shielding layer or another independent conductive structure or one ground contact and then comparing the measured resistance value with a predetermined reference value, the EMI shielding performance of the package structure is determined. | 10-03-2013 |
20140132350 | ELECTRONIC SYSTEM, RF POWER AMPLIFIER AND TEMPERATURE COMPENSATION METHOD THEREOF - A radio frequency (RF) power amplifier is disclosed. The RF radio power amplifier includes a bias current generating unit, a first impedance unit, a second impedance unit, a third impedance unit and an output stage unit. The bias current generating unit receives a reference voltage. There is a first voltage with negative temperature coefficient between the first impedance unit and the second impedance unit, and the second unit receives a ground current. There is a second voltage between the third impedance unit and the second impedance unit, and the second voltage is a partial voltage of the first voltage. The bias current generating unit outputs a bias current with positive temperature coefficient according to the second voltage. The output stage unit receives an input current. The bias current is a sum of the input current with positive temperature coefficient and the ground current. | 05-15-2014 |
20140153670 | ELECTRONIC SYSTEM, RF POWER AMPLIFIER AND TEMPERATURE COMPENSATION METHOD THEREOF - A radio frequency (RF) power amplifier is disclosed. The RF power amplifier includes an adder circuit, an output-stage circuit and a differential circuit. The adder circuit has a first ratio and a second ratio, and receives a reference voltage and a feedback voltage so as to output an adder voltage after an operation, wherein the feedback voltage is a voltage with a negative temperature coefficient, and the reference voltage is sum of a first voltage with a negative temperature coefficient and a second voltage with positive temperature coefficient. The output-stage circuit is used for providing the feedback voltage. The differential circuit has a first multiplier factor, and the differential circuit makes the first multiplier factor be multiplied with the adder voltage so as to provide a voltage to the output-stage circuit. The RF power amplifier stabilizes an output current through adjusting the temperature coefficient of the reference voltage. | 06-05-2014 |
20140159819 | ELECTRONIC SYSTEM, RF POWER AMPLIFIER AND OUTPUT POWER COMPENSATION METHOD THEREOF - A radio frequency (RF) power amplifier is disclosed. The power amplifier includes an output stage circuit, an exponential type bias circuit and a voltage-current transformation circuit. The output stage circuit receives a first system voltage and outputs an output current. The exponential type bias circuit receives a bias current, wherein a relationship between the bias current and output current is exponential, and when the bias current is zero current, and the output current is zero current. The voltage-current transformation circuit transforms the first system voltage into a second current so that the bias current is in proportion to the first system voltage, and thus the relationship between the output current and the first system voltage is exponential. The bias current is equal to times of the sum of the first current and the second current. | 06-12-2014 |
20140167854 | ELECTRONIC SYSTEM - RADIO FREQUENCY POWER AMPLIFIER AND METHOD FOR SELF-ADJUSTING BIAS POINT - A radio frequency (RF) power amplifier is disclosed. The RF power amplifier includes a bias circuit, an output stage circuit and dynamic bias controlling circuit. The bias circuit receives a system voltage and the bias circuit provides a working voltage according to the system voltage. The output stage circuit receives the working voltage so as to work at an operation bias point. The dynamic bias controlling circuit receives the working voltage and outputs a compensation voltage to the bias circuit according to a variation of the working voltage. When the input power increases and makes the working voltage decreases so as to shift the operation bias point, the bias circuit adjusts the working voltage upward so as to recover the operation bias point according to the compensation voltage received. | 06-19-2014 |
20140327482 | RADIO FREQUENCY POWER AMPLIFIER WITH NO REFERENCE VOLTAGE FOR BIASING AND ELECTRONIC SYSTEM - A radio frequency (RF) power amplifier with no reference voltage for biasing is disclosed. The RF power amplifier includes a three-terminal current source circuit, a current mirror circuit and an output-stage circuit. The three-terminal current source circuit receives a first system voltage and accordingly outputs a first current and a second current, and a source voltage exists between a first output terminal of the first current and a second output terminal of the second current. The current mirror circuit receives the first current and the second current and accordingly generates a bias current. The output-stage circuit receives the bias current so as to work at an operation point. The RF power amplifier utilizes the source voltage of the three-terminal current source circuit so the first system voltage is between a first voltage and a second voltage, and then the output-stage circuit outputs an output current which does not vary with a deviation of the first system voltage also with temperature compensation. | 11-06-2014 |
20140354259 | BANDGAP REFERENCE VOLTAGE GENERATING CIRCUIT AND ELECTRONIC SYSTEM USING THE SAME - A bandgap reference voltage generating circuit for providing a reference voltage is disclosed. The bandgap reference voltage generating circuit includes four-terminal current source circuit, a regulator circuit and a temperature-compensating circuit. The four-terminal current source circuit outputs a first voltage, a second voltage and a first current which are independent of variation of a first system voltage. The regulator circuit receives the first voltage and the second voltage and when the first system voltage is larger than a threshold voltage value, the regulator circuit outputs the reference voltage independent of variation of the first system voltage via voltage-difference between the first voltage and the second voltage. The temperature-compensating circuit receives the first current and compensates a temperature curve of the reference voltage outputted from the regulator circuit. | 12-04-2014 |
20140368277 | RADIO FREQUENCY POWER AMPLIFIER AND ELECTRONIC SYSTEM - A radio frequency (RF) amplifier is disclosed. The RF power amplifier includes a bias circuit, an output-stage circuit and a RF compensation circuit. When a first system voltage is larger than a first voltage threshold value, the bias circuit generates a first current rising slightly. When first system voltage is larger than second voltage threshold value, the RF compensation circuit receives a second circuit rising slightly transmitted from the bias circuit. When the first system voltage is in an operation voltage range, the first current is larger than the second circuit so as to a quiescent operating current of the RF power amplifier is independent of change of the first system voltage. When the first system voltage is larger than a third voltage threshold value, the first current is equal to the second current so as to have the bias current being a zero current to protect the RF power amplifier from over-voltage. | 12-18-2014 |
20150244053 | TUNABLE RADIO FREQUENCY COUPLER AND MANUFACTURING METHOD THEREOF - A tunable radio frequency (RF) coupler and manufacturing method thereof are provided. The tunable RF coupler includes an insulating layer, a first transmission line and a second transmission line. The second transmission line is disposed corresponding to the first transmission line and the insulating layer is disposed between the first transmission line and the second transmission line. The second transmission line includes a plurality of segments separated from each other and arranged along the extension path of the first transmission line. At least one wire is configured to establish an electrical connection between at least two segments, such that the two segments are electrically conductive to each other through the wire. | 08-27-2015 |
20150244327 | AMPLIFIER CIRCUIT, BIASING BLOCK WITH OUTPUT GAIN COMPENSATION THEREOF, AND ELECTRONIC APPARATUS - An exemplary embodiment of the present disclosure illustrates an amplifier circuit comprising an amplifier block and a biasing block. The amplifier block is used to receive an input signal and amplify the input signal to generate an output signal. The a biasing block coupled to the amplifier block is used to provide biasing voltages to bias the amplifier block, and compensate an output gain of the amplifier block before the output gain of the amplifier block is compressed, so as to extend a P1 dB compression point of the amplifier block, wherein the biasing currents are substantially independent to temperature and/or system voltage variation. | 08-27-2015 |
20150263675 | LOW NOISE AMPLIFIER AND RECEIVER - A low noise amplifier is disclosed. The low noise amplifier comprises a current mirror circuit, a bias circuit, a cascode amplifying circuit and a power gain compensating circuit. The current mirror circuit is used for providing a mapping current. The bias circuit is used for receiving a mapping current and outputting a first bias voltage and a second bias voltage according to the mapping current. The cascode amplifying circuit respectively receives the first bias voltage and the second bias voltage, and accordingly to work at an operation bias point. The power gain compensating circuit is used for receiving a RF output signal and accordingly outputs a gain compensating signal to the current mirror circuit so as to dynamically adjust current value of the mapping current and further to compensates power gain of the low noise amplifier in order to increase linearity. | 09-17-2015 |
20150280672 | LOW NOISE AMPLIFIER AND RECEIVER - A low noise amplifier is disclosed. The low noise amplifier comprises a current mirror circuit, a bias circuit, a cascode amplifying circuit and a power gain compensating circuit. The current mirror circuit is used for providing a first current and third current. The bias circuit is used for receiving a first current and third current and outputting a first bias voltage and a second bias voltage according to the first current and third current. The cascode amplifying circuit respectively receives the first bias voltage and the second bias voltage, and accordingly to work at an operation bias point. The power gain compensating circuit is used for receiving a RF output signal and accordingly outputs a gain compensating signal to the current mirror circuit so as to dynamically adjust current value of the first current and third current and further to compensates power gain of the low noise amplifier in order to increase 1 dB gain compression point (P1dB). | 10-01-2015 |
Patent application number | Description | Published |
20150077389 | TOUCH RECOGNITION METHOD AND SYSTEM FOR A CAPACITIVE TOUCH APPARATUS - The present invention discloses a method and system for touch signal recognition adapted to be used in a capacitive touch panel or apparatus. In order to achieve an objection of enhancement of a touch signal for recognition and getting rid of noise impact simultaneously, the present invention discloses a touch recognition method that actually includes two different measurement cycles to acquire two different sample voltage values. Consequently, noise impact can be removed by calculation of a sample voltage value difference between two different sample voltage values, at the same time, and the sample voltage value difference can provide a double magnitude as disclosed in the prior art to enhance accuracy for recognizing a user touch input while preventing from influence of noise. | 03-19-2015 |
20150123677 | Handling of electromagnetic interference in an electronic apparatus - The present invention provides a control module and a method operable in a touch-sensitive apparatus for measuring noise, wherein the touch-sensitive apparatus comprises a touch-sensitive module having a plurality of first electrodes and a plurality of second electrodes that intersect in multiple regions of the touch sensitive module, said method comprising the steps of: disconnecting the first electrodes from a driving voltage source; and acquiring a plurality of voltage values of noise by measuring a plurality of voltage signals associated with the second electrodes over a plurality of measurement cycles at a predetermined operating frequency during the first electrodes without a driving voltage. | 05-07-2015 |
20150123950 | Handling of electromagnetic interference in an electronic apparatus - The present invention provides a touch-sensitive apparatus and a method for determining a coordinate position in response to a proximity detection for the touch-sensitive apparatus. The method comprises the steps of: evaluating a plurality of designed measurement modes by measuring noise over a plurality of measurement cycles when a proximity event on the touch-sensitive apparatus has been detected; selecting an optimal measurement mode from the plurality of designed measurement modes; assigning the optimal measurement mode to be a working measurement mode; performing the proximity detection for the touch-sensitive apparatus in use of the working measurement mode; and calculating the coordinates of the touched position based on results obtained with the working measurement mode. | 05-07-2015 |
20160048258 | TOUCH SENSITIVE DEVICE, SYSTEM and METHOD THEREOF - A touch sensitive detecting method, applicable to a touch panel or screen, comprises: setting a sensing electrode to floating; after the sensing electrode is set to floating, setting at least one non-measuring sensing electrode to a sensing high voltage; measuring the voltage of the sensing electrode; setting the sensing electrode to a ground voltage and stopping measurement; and determining whether an externally conducted object is approximating or touching the touch panel or screen nearby the sensing electrode by comparing a difference between a threshold voltage and the measured voltage of the sensing electrode. | 02-18-2016 |
Patent application number | Description | Published |
20150137423 | THREE-DIMENSIONAL PRINTING METHOD - A three-dimensional printing method for forming a three-dimensional object on a base is provided. The method comprises providing a model library comprising at least one supporting member, selecting the at least one supporting member from the model library and disposing the at least one supporting member onto the base. The three-dimensional object is printed over the base and the at the least supporting member, and the three-dimensional object has an overhanging portion relative to the base and the at least one supporting member is filled between the overhanging portion and the base. | 05-21-2015 |
20150153974 | PRINTING SYSTEM AND DATA TRANSMISSION METHOD THEREOF - A printing system and a data transmission method thereof are provided. The printing system includes a peripheral unit and a controller. The peripheral unit is configured to execute a data printing function and includes a digital data. The controller is coupled to the peripheral unit. The controller converts a digital control command to obtain an analog control signal, and transmits the analog control signal to the peripheral unit. The peripheral unit converts the analog control signal into the digital control command when the analog control signal is received by the peripheral unit. The peripheral unit converts a corresponding digital data into an analog signal according to the digital control command to transmit the analog signal to the controller. | 06-04-2015 |
20150290879 | THREE-DIMENSIONAL PRINTING MODULE AND THREE-DIMENSIONAL PRINTING APPARATUS USING THE SAME - A three-dimensional (3D) printing module including a tank filled with a liquid forming material, a top cover assembled on the tank to close the tank, a modeling platform assembled to the cover, and a first tenon movably disposed in the cover is provided. The modeling platform is immersed in the liquid forming material in the tank. When the first tenon is driven along a second axis, the cover and the modeling platform are driven along a first axis to open the tank. A 3D printing apparatus is also provided. | 10-15-2015 |
20150321421 | METHOD FOR DETECTING CHARACTERISTIC OF FORMING MATERIAL AND THREE-DIMENSIONAL PRINTING APPARATUS - A method for detecting a characteristic of a forming material and a three-dimensional printing apparatus are provided. The three-dimensional printing apparatus includes a tank filled with a liquid forming material, and the method includes the following. The tank is controlled to swing to cause a wave motion on a liquid surface of the liquid forming material. The wave motion of the liquid forming material is detected to obtain detection waveform information. The detection waveform information and sample waveform information are compared with each other to obtain a characteristic comparison result. A predefined operation is executed according to the characteristic comparison result. | 11-12-2015 |
20150328841 | FORMING DEVICE FOR THREE-DIMENSIONAL PRINTING MACHINE, AND A THREE-DIMENSIONAL PRINTING MACHINE - A forming device for a three-dimensional printing machine is connected to a height adjusting mechanism of the three-dimensional printing machine, and is driven by the height adjusting mechanism to move vertically. The forming device includes an universal joint, a forming platform, a coupling shaft interconnecting the universal joint and the forming platform, and a clamping mechanism. The clamping mechanism includes a clamping arm adapted to interconnect the height adjusting mechanism and the universal joint, and having first and second arm portions movable relative to each other between a locking state to tightly clamp the universal joint, and a releasing state to release the universal joint so that the forming platform is movable relative to the clamping mechanism. | 11-19-2015 |
20160059485 | THREE-DIMENSIONAL PRINTING APPARATUS AND METHOD FOR THREE-DIMENSIONAL PRINTING - A method for three-dimensional printing for forming a three-dimensional structure on a moving platform is provided. The three-dimensional structure includes a shell portion and a foamy filling portion. The method includes the following: a digital shell model of the three-dimensional structure is built. Next, the digital shell model is sliced into a plurality of cross-section information. Next, a corresponding liquid forming material is cured on the moving platform according to the cross-section information to form a plurality of shell layers. Next, foaming process is performed on the liquid forming material to form a foamy forming material. Next, the foamy forming material located within the corresponding shell layers is cured to form a plurality of foamy filling layers. Afterward, the shell layers and the foamy filling layers are alternately formed on the moving platform and stacked to form the three-dimensional structure. A three-dimensional printing apparatus adopting the method is also provided. | 03-03-2016 |
20160096332 | THREE DIMENSIONAL PRINTING APPARATUS AND PRINTING METHOD THEREOF - A three-dimensional printing apparatus and a printing method thereof are provided. The three-dimensional printing apparatus includes a tank, a movable platform, a light source module, and a controller. The bottom of the tank includes an irradiated area and a non-irradiated area. The movable platform is movably disposed above the tank. The light source module is disposed under the tank and only provides light to the irradiated area to irradiate a liquid-formation material. The controller controls the movable platform to move along a first axis direction, such that at least one layer object of a three-dimensional object is cured on the movable platform layer by layer. The layer object is composed of object sections. During a period of forming one layer object, the controller controls the movable platform to move on a horizontal plane, such that the object sections of the layer object are cured sequentially above the irradiated area. | 04-07-2016 |
Patent application number | Description | Published |
20080225830 | CIRCUIT WITH GENERATING PHONE-CALL RING VIA COMPUTER SYSTEM AND INTERNET PHONE SYSTEM USING THE CIRCUIT - An internet phone system is implemented in a computer system, including an internet-phone software unit, for storing a software used by the computer system to operate as an internet phone. An audio-file storage software unit is for storing a plurality of audio files. A USB (Universal Serial Bus) audio interface software unit is coupled with the internet-phone software unit and the audio-file storage unit. A USB audio apparatus is coupled to the audio interface unit, and comprising at least a microphone and a speaker. Wherein, the USB audio interface unit stores a software for selecting one of the audio files to serve as the phone-call ring, and for driving the speaker in the USB audio apparatus by the computer system for generating ringing sound for an incoming call. | 09-18-2008 |
20100161856 | USB AUDIO AND MOBILE AUDIO SYSTEM USING USB AUDIO CONTROLLER - A USB audio controller includes an USB interface unit, an audio interface unit, a storage interface unit, and a processing unit. The USB interface unit is used to connect to a USB bus for communicating with a host by a communication information. The audio interface unit is used to connect to at least one audio device for communicating with an audio signal. The storage unit is used to connect to a memory unit for communicating storage information. The processing unit is for processing the communicating information and audio signal. | 06-24-2010 |
20100161857 | USB AUDIO CONTROLLER - An USB audio controller includes an USB interface unit, an audio interface unit, a storage interface unit, and a processing unit. The USB interface unit is used to connect to an USB bus for communicating with a host by a communication information. The audio interface unit is used to connect to at least one audio device for communicating with an audio signal. The storage interface unit is used to connect to a memory unit for communicating storage information. The processing unit is for processing the communicating information, storage information, or audio signal. | 06-24-2010 |
Patent application number | Description | Published |
20130268195 | Itinerary Planning System and Method Thereof - The present invention provides an itinerary planning system and an itinerary planning, estimating and automatic producing method, wherein the itinerary planning system including an itinerary displaying board for displaying an itinerary, a general information displaying module for displaying a general information and a geographic information displaying module for displaying a geographic information, wherein an interaction existing among them. The itinerary planning system is capable of planning an itinerary, estimating the best sequence of the itinerary, sequencing the itinerary automatically according to the interest of the user, and editing the same itinerary by the multi-people real-timely and synchronously, to make the itinerary planning system of the present invention is more convenience for the user to use the system. | 10-10-2013 |
20130268306 | SCHEDULE ARRANGEMENT SYSTEM AND METHOD FOR TRIPS MATCHING, INTEGRATION AND OUTPUT - The present invention provides a schedule arrangement system and a method for trips matching, integration and output, the schedule arrangement system includes at least one information of an itinerary displaying board displaying an itinerary; a general displaying module displaying the general; a geographic displaying module displaying geographic; and at least an interaction existing thereamong for assisting the users in completing their schedule plans. In one embodiment, the schedule arrangement system further includes a matching system. In another embodiment, the schedule arrangement system further includes an integration system of schedule arrangement and resource reservation. In still another embodiment, the schedule arrangement system further includes a personalized travel information automatic output system. | 10-10-2013 |
Patent application number | Description | Published |
20090198345 | CALCIUM SILICATE-BASED COMPOSITE CEMENT AND MANUFACTURING METHOD THEREOF - The present invention provides a method for producing calcium silicate-based bone cement and a composition produced by the method. It further provides a novel mixture for bone tissue repair. | 08-06-2009 |
20100196514 | CALCIUM SILICATE-BASED COMPOSITE CEMENT AND METHODS FOR THE PREPARATION - The present invention provides a method for producing calcium silicate-based bone cement and a composition produced by the method. It further provides a novel composition for bone tissue repair. | 08-05-2010 |
20110232533 | METHOD FOR PRODUCING CALCIUM SILICATE-BASED BONE CEMENT - One aspect of the present invention provides a method for producing calcium silicate-based bone cement, including the steps of mixing calcium salt with silicohydrides to form a first mixture; processing the first mixture with a sol-gel process to form a second mixture; heating the second mixture to form a dried mixture; grinding the second mixture into powder; and adding the powder to water or phosphate solution. | 09-29-2011 |
20120330434 | BILAYERED BONE GRAFT DEVICE - A bilayered bone graft device includes a core portion comprising deminernalized gelatin and a shell portion surrounding the core portion. The shell portion includes a calcium silicate and the deminernalized gelatin in a range of 1 to 30 weight percent, and the calcium silicate has a molar ratio of calcium to silicon ranging from 10 to 0.1. The core portion and the shell portion are bound by the deminernalized gelatin without using a binder. In one embodiment of the present invention, the core portion is configured to provide buffering for receiving an insertion, and the shell portion is configured to provide a load-bearing structure. | 12-27-2012 |
Patent application number | Description | Published |
20090114436 | SUBSTRATE STRUCTURE - A substrate structure is provided. A plurality of solder pads is positioned on a substrate. A solder mask covers the substrate and has a plurality of openings to respectively expose portions of the solder pads, wherein the openings have the shape of a polygon of at least five sides. | 05-07-2009 |
20140367837 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MAKING THE SAME - The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer. | 12-18-2014 |
20140367852 | SUBSTRATE HAVING PILLAR GROUP AND SEMICONDUCTOR PACKAGE HAVING PILLAR GROUP - The present disclosure provides a substrate and a semiconductor package. The substrate includes a body, at least one pad group, a plurality of traces and at least one pillar group. The pad group includes a plurality of pads. Each pad has at least one inner side and at least one outer side. The inner side of a first pad is faced to the inner side of an adjacent second pad with a spaced section between. Each pillar group includes a plurality of pillars disposed on respective ones of the pads. The use of pad groups having multiple pads on which to form pillars allows an increase in the number of the pillars available in a given area so as to increase the amount of I/O connections. Furthermore, for a given number of I/O connections, the area occupied by the pads, pillars and traces can be reduced. | 12-18-2014 |
Patent application number | Description | Published |
20110227220 | STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced. | 09-22-2011 |
20110241192 | Wafer-Level Semiconductor Device Packages with Stacking Functionality - Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices. | 10-06-2011 |
20110241193 | Semiconductor Device Packages with Fan-Out and with Connecting Elements for Stacking and Manufacturing Methods Thereof - An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect extending substantially vertically from the conductive layer; (3) a semiconductor device adjacent to the interconnection unit and electrically connected to the conductive layer; (4) a package body: (a) substantially covering an upper surface of the interconnection unit and the device; and (b) defining an opening adjacent to an upper surface of the package body and exposing an upper surface of the interconnect; and (5) a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package. The upper surface of the interconnect defines a first plane above a second plane defined by at least a portion of the upper surface of the interconnection unit, and below a third plane defined by the upper surface of the package body. | 10-06-2011 |
20130171774 | STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced. | 07-04-2013 |
20140175663 | SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIA AND MANUACTURING PROCESS - In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore. | 06-26-2014 |
Patent application number | Description | Published |
20120043955 | Bandgap Reference Circuit and Bandgap Reference Current Source - The present invention provides a bandgap reference circuit. The bandgap reference circuit includes a first bipolar junction transistor, a first resistor, for generating a proportional to absolute temperature current, a second resistor, for generating a complementary to absolute temperature current, a first operational amplifier, coupled with the first bipolar junction transistor and the first resistor, a second operational amplifier, coupled with the first bipolar junction transistor and the second resistor, and a zero temperature correlated current generator, for summing the proportional to absolute temperature current and the complementary to absolute temperature current, to generate a zero temperature correlated current. | 02-23-2012 |
20120098506 | Low Noise Current Buffer Circuit and I-V Converter - A low noise current buffer circuit includes a first transistor, for receiving an input current, a second transistor, for draining a first current from a drain of the second transistor according to the input current received by the first transistor, a third transistor, for outputting first current, a fourth transistor, for outputting a second current to an output resistor, to generate an output voltage, and a feedback capacitor, for eliminating impacts of noise of a system voltage on the output voltage. | 04-26-2012 |
20120126616 | REFERENCE VOLTAGE GENERATION CIRCUIT AND METHOD - A reference voltage generation circuit includes: a bandgap reference circuit, generating a plurality of initial currents with different temperature coefficients; a base voltage generation circuit, combining the initial current into a combined current, and converting the combined current into one or more base voltages; a bias current source circuit, generating one or more bias currents based on at least one of the initial currents; and one or more regulating output circuit, each converting a respective one of the one or more bias currents into an increment voltage and adding the increment voltage to the base voltage to generate a respective output voltage. Each output voltage may have its respective temperature coefficient. | 05-24-2012 |
20130113776 | Power Management Circuit and Gate Pulse Modulation Circuit Thereof - A power management circuit for a liquid crystal display device is disclosed. The power management circuit includes one or more power generating circuits, for receiving one or more input voltages and generating one or more output voltages, respectively; a gate pulse modulation circuit, coupled between a gate high-level voltage source and a discharging control terminal, for generating a gate control signal; and a discharging controller, coupled to the discharging control terminal, for providing a discharging path for the gate pulse modulation circuit, wherein one of the gate pulse modulation circuit and the discharging controller is further coupled to a power supply such that the gate pulse modulation circuit discharges to the power supply during a gate discharging period, and the power supply is one of the one or more input voltages and the one or more output voltages. | 05-09-2013 |
20130222051 | Charge Pump Device and Driving Capability Adjustment Method Thereof - A charge pump device is disclosed. The charge pump device includes a driving stage, for generating a driving signal corresponding to a driving capability; a charge pump circuit, for generating an output voltage according to the driving signal; a comparing circuit, comprising a first comparator for comparing the output voltage and a first reference voltage to generate a first comparing result; an overload detection circuit, for generating a detection result according to at least one of the first comparing result and the output voltage; and a driving capability control circuit, coupled between the overload detection circuit and the driving stage for controlling the driving capability corresponding to the driving signal according to the detection result. | 08-29-2013 |
20130342265 | Charge Pump Device - A charge pump device is disclosed. The charge pump device includes a driving stage, for generating a driving signal corresponding to a driving capability; a charge pump circuit, for generating an output voltage according to the driving signal; a comparing circuit, comprising a first comparator for comparing the output voltage and a first reference voltage to generate a first comparing result; an overload detection circuit, for generating a detection result according to at least one of the first comparing result and the output voltage; and a driving capability control circuit, coupled between the overload detection circuit and the driving stage for controlling the driving capability corresponding to the driving signal according to the detection result. | 12-26-2013 |
20150061635 | VOLTAGE CONVERTING INTEGRATED CIRCUIT - A voltage converting integrated circuit includes a first switch, a second switch, a third switch, a fourth switch, and a control circuit. The first switch is coupled between a first voltage pin and a first switch pin. The second switch is coupled between a second voltage pin and a second switch pin. The third switch is coupled between the first switch pin and a third voltage pin. The fourth switch is coupled between the second switch pin and a reference ground. The first to the fourth switches are controlled by a control signal to be turned on or off. The control circuit is coupled to the first to the fourth switches for receiving a mode setting signal and the control circuit generates a control signal according to the mode setting signal. | 03-05-2015 |