Patent application number | Description | Published |
20090111243 | SOI SUBSTRATES WITH A FINE BURIED INSULATING LAYER - A method of producing a semiconductor structure having a buried insulating layer having a thickness between 2 and 25 nm, by: forming at least one insulating layer on a surface of a first or second substrate, or both, wherein the surfaces are free from an insulator or presenting a native oxide layer resulting from exposure of the substrates to ambient conditions; assembling the first and second substrates; and thinning down the first substrate, in order to obtain the semiconductor structure. In this method, the insulating layer forming stage is a plasma activation based on an oxidizing or nitriding gas. | 04-30-2009 |
20110012200 | SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER - Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 10 | 01-20-2011 |
20110165758 | METHOD FOR MAKING A STRUCTURE COMPRISING A STEP FOR IMPLANTING IONS IN ORDER TO STABILIZE THE ADHESIVE BONDING INTERFACE - The invention relates to a method for making a structure for use ion applications in the fields of electronics, optics or optoelectronics. The structure includes a thin layer of semiconducting material on a supporting substrate. The method includes bonding the thin layer onto the supporting substrate by molecular adhesion at a bonding interface to obtain a structure; implanting ions at the bonding interface to transfer atoms from the thin layer to transfer atoms between the thin layer and the supporting substrate or vice versa; and heat-treating the structure in order to stabilize the bonding interface. | 07-07-2011 |
20110177673 | METHOD FOR PRODUCING A STACK OF SEMI-CONDUCTOR THIN FILMS - A method for producing a stacked structure having an ultra thin buried oxide (UTBOX) layer therein by forming an electrical insulator layer on a donor substrate, introducing elements into the donor substrate through the insulator layer, forming an electrical insulator layer, on a second substrate, and bonding the two substrates together to form the stack, with the two insulator layers limiting the diffusion of water and forming the UTBOX layer between the two substrates at a thickness of less than 50 nm, wherein the donor oxide layer has, during bonding, a thickness at least equal to that of the bonding oxide layer. | 07-21-2011 |
20110183493 | PROCESS FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE - The present invention relates to a process for manufacturing a structure comprising a germanium layer ( | 07-28-2011 |
20110193201 | METHOD TO FABRICATE AND TREAT A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE, ENABLING DISPLACEMENT OF DISLOCATIONS, AND CORRESPONDING STRUCTURE - The present invention notably concerns a method to fabricate and treat a structure of semiconductor-on-insulator type, successively comprising a carrier substrate ( | 08-11-2011 |
20110207295 | METHOD OF DETACHING SEMI-CONDUCTOR LAYERS AT LOW TEMPERATURE - A method for producing a structure having an ultra thin buried oxide (UTBOX) layer by assembling a donor substrate with a receiver substrate wherein at least one of the substrates includes an insulating layer having a thickness of less than 50 nm that faces the other substrate, conducting a first heat treatment for reinforcing the assembly between the two substrates at temperature below 400° C., and conducting a second heat treatment at temperature above 900° C., wherein the exposure time between 400° C. and 900° C. between the heat treatments is less than 1 minute and advantageously less than 30 seconds. | 08-25-2011 |
20110266651 | METHOD FOR MANUFACTURING COMPONENTS - The invention relates to a method for manufacturing components on a mixed substrate. It comprises the following steps: —providing a substrate of the semiconductor-on-insulator (SeOI) type comprising a buried oxide layer between a supporting substrate and a thin layer, —forming in this substrate a plurality of trenches opening out at the free surface of the thin layer and extending over a depth such that it passes through the thin layer and the buried oxide layer, these primary trenches delimiting at least one island of the SeOI substrate, —forming a mask inside the primary trenches and as a layer covering the areas of the free surface of the thin layer located outside the islands, —proceeding with heat treatment for dissolving the buried oxide layer present at the island, so as to reduce the thickness thereof. | 11-03-2011 |
20110275226 | PROCESS TO DISSOLVE THE OXIDE LAYER IN THE PERIPHERAL RING OF A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE - The invention concerns a process to treat a structure of semiconductor-on-insulator type structure of a carrier substrate, an oxide layer and a thin layer of a semiconductor material, wherein the structure having a peripheral ring in which the oxide layer is exposed, and the process includes the application of a main thermal treatment in a neutral or controlled reducing atmosphere. The method includes a step to cover at least an exposed peripheral part of the oxide layer, prior to the main thermal treatment, this latter treatment being conducted under controlled time and temperature conditions so as to urge at least part of the oxygen in the oxide layer to diffuse through the thin semiconductor layer, leading to controlled reduction of the thickness of the oxide layer. | 11-10-2011 |
20110278597 | METHOD OF PRODUCING A LAYER OF CAVITIES - A method of producing a layer of cavities in a structure comprises at least one substrate formed from a material that can be oxidized or nitrided, the method comprising the following steps: implanting ions into the substrate in order to form an implanted ion concentration zone at a predetermined mean depth; heat treating the implanted substrate to form a layer of cavities at the implanted ion concentration zone; and forming an insulating layer in the substrate by thermochemical treatment from one surface of the substrate, the insulating layer that is formed extending at least partially into the layer of cavities. | 11-17-2011 |
20120094469 | PROCESS FOR REALISING A CONNECTING STRUCTURE - The present invention relates to a process for realizing a connecting structure in a semiconductor substrate, and the semiconductor substrate realized accordingly. The semi-conductor substrate has at least a first surface, and is foreseen for a 3D integration with a second substrate along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value. This process includes growing a diffusion barrier structure for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, wherein a first end surface, being the most outward surface of the diffusion barrier structure and being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure can have a length, in the direction of the lateral misalignment, the length being dependent on the misalignment value, wherein the length of the diffusion barrier structure is chosen such that in a 3D integrated structure a diffusion of elements out of a conductive layer of the second substrate is prevented in the integrated state. | 04-19-2012 |
20120094496 | Process For Locally Dissolving The Oxide Layer In A Semiconductor-On-Insulator Type Structure - A process for treating a semiconductor-on-insulator type structure that includes, successively, a support substrate, an oxide layer and a thin semiconductor layer. The process includes formation of a silicon nitride or silicon oxynitride mask on the thin semiconductor layer to define exposed areas at the surface of the layer which are not covered by the mask, and which are arranged in a desired pattern; and application of a heat treatment in a neutral or controlled reducing atmosphere and under controlled conditions of temperature and time to induce at least a portion of the oxygen of the oxide layer to diffuse through the thin semiconductor layer, thereby resulting in the controlled reduction in the oxide thickness in the areas of the oxide layer corresponding to the desired pattern. The mask is formed so as to be at least partially buried in the thickness of the thin semiconductor layer. | 04-19-2012 |
20120231636 | PROCESS FOR TREATING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE - A process for treating a semiconductor-on-insulator structure that has, in succession, a support substrate, a layer of an oxide or oxynitride of a semiconductor material, and a thin semiconductor layer of the semiconductor material. The process includes providing, on the surface of the thin layer, a mask defining exposed regions of the thin layer; providing a layer of nitride or oxynitride of the semiconductor material on the exposed regions of the thin layer; and applying a heat treatment causing at least some of the oxygen in the oxide or oxynitride layer to diffuse through the exposed regions. The nitride or oxynitride layer is provided at a thickness sufficient to provide a ratio of the rate of oxygen diffusion though the exposed regions to that through the regions covered with the mask that is greater than 2. | 09-13-2012 |
20120252162 | METHODS FOR BONDING SEMICONDUCTOR STRUCTURES INVOLVING ANNEALING PROCESSES, AND BONDED SEMICONDUCTOR STRUCTURES FORMED USING SUCH METHODS - Methods of bonding together semiconductor structures include annealing a first metal feature on a first semiconductor structure, bonding the first metal feature to a second metal feature of a second semiconductor structure to form a bonded metal structure that comprises the first metal feature and the second metal feature, and annealing the bonded metal structure. Annealing the first metal feature may comprise subjecting the first metal feature to a pre-bonding thermal budget, and annealing the bonded metal structure may comprise subjecting the bonded metal structure to a post-bonding thermal budget that is less than the pre-bonding thermal budget. Bonded semiconductor structures are fabricated using such methods. | 10-04-2012 |
20120252189 | METHODS FOR BONDING SEMICONDUCTOR STRUCTURES INVOLVING ANNEALING PROCESSES, AND BONDED SEMICONDUCTOR STRUCTURES AND INTERMEDIATE STRUCTURES FORMED USING SUCH METHODS - Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods. | 10-04-2012 |
20120329243 | PROCESS FOR FABRICATING A SEMICONDUCTOR STRUCTURE EMPLOYING A TEMPORARY BOND - The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate. | 12-27-2012 |
20130294038 | ELECTRONIC DEVICE FOR RADIOFREQUENCY OR POWER APPLICATIONS AND PROCESS FOR MANUFACTURING SUCH A DEVICE - The invention relates to an electronic device for radio frequency or power applications, comprising a semiconductor layer supporting electronic components on a support substrate, wherein the support substrate comprises a base layer having a thermal conductivity of at least 30 W/m K and a superficial layer having a thickness of at least 5 μm, the superficial layer having an electrical resistivity of at least 3000 Ohm·cm and a thermal conductivity of at least 30 W/m K. The invention also relates to two processes for manufacturing such a device. | 11-07-2013 |
20140015023 | SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER - Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 10 | 01-16-2014 |
20140030877 | PROCESS TO DISSOLVE THE OXIDE LAYER IN THE PERIPHERAL RING OF A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE - A process for avoiding formation of a Si—SiO | 01-30-2014 |
20140326416 | METHOD FOR SEPARATING A LAYER FROM A COMPOSITE STRUCTURE - The disclosure relates to a method for separating a layer from a composite structure, the structure comprising a composite stack formed from at least a support substrate, which is partially transparent at a determined wavelength, the layer to be separated and a separation layer interposed between the support substrate and the layer to be separated, the method comprising irradiation of the separation layer through the support substrate by means of incident light ray at the determined wavelength in order to induce weakening or separation by exfoliation of the separation layer, the light ray being inclined so as to form an angle of incidence Θ such that θ>θ | 11-06-2014 |