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Dhong, CA
Sang Dhong, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100002482 | MEMORY DEVICE AND METHOD - A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor. | 01-07-2010 |
| 20100002502 | MEMORY DEVICE AND METHOD OF REFRESHING - A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor. | 01-07-2010 |
| 20100146330 | MEMORY DEVICE AND METHOD THEREOF - An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits. | 06-10-2010 |
Sang H. Dhong, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090112550 | System and Method for Generating a Worst Case Current Waveform for Testing of Integrated Circuit Devices - A system and method for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison. | 04-30-2009 |
| 20100102867 | SENSE AMPLIFIER BASED FLIP-FLOP - A sense amplifier based flip-flop having built-in logic functions. The flip-flop includes a first and second input circuits configured to cause complementary first and second logic values to be provided on first and second logic nodes, respectively. The flip-flop further includes a sense circuit configured to sense and capture the first and second logic values on first and second capture nodes, respectively, during an evaluation phase, and a precharge circuit configured to precharge the first and second logic node and the first and second capture nodes during a precharge phase. The flip-flop also includes a noise immunity circuit, configured to, during the evaluation phase, become active subsequent to the sense circuit capturing the first and second logic values, wherein, when activated, the noise immunity circuit prevents floating voltages on the first and second logic nodes. | 04-29-2010 |
| 20100144106 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATING THE SAME - A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor. | 06-10-2010 |
Sang Hoo Dhong, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090116307 | LEVEL SHIFTER FOR BOOSTING WORDLINE VOLTAGE AND MEMORY CELL PERFORMANCE - A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation. | 05-07-2009 |
| 20090121747 | Maintaining Circuit Delay Characteristics During Power Management Mode - A system and method for maintaining circuit delay characteristics during power management mode. The method for maintaining circuit delay characteristics during power management mode continually toggles the clock distribution circuits at a frequency sufficiently low that it does not significantly impact chip power dissipation. The clock frequency used to toggle the clock distribution circuits is high enough to minimize the asymmetrical stress on the clock buffer transistors so that both P and N device characteristics equally change over time. | 05-14-2009 |
| 20090199036 | LSSD compatibility for GSD unified global clock buffers - A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal. | 08-06-2009 |