| Patent application number | Description | Published |
|---|
| 20090040842 | Enhanced write abort mechanism for non-volatile memory - In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal. | 02-12-2009 |
| 20090040843 | Enhanced write abort mechanism for non-volatile memory - In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal. | 02-12-2009 |
| 20090080249 | Non-volatile memory cell endurance using data encoding - A method and apparatus for storing an n-bit (for n>=2) data block in an array of non-volatile memory cells utilizes a predetermined n+k-bit (for k>=1) encoding selected to reduce the number of programmed cells required to store the n-bit data block. | 03-26-2009 |
| 20090085221 | Multi-host interface controller with USB PHY/analog functions integrated in a single package - In a first embodiment, an apparatus and a method of fabrication thereof includes a substrate, a controller formed on a first integrated circuit (IC) die and disposed on the substrate, a second IC die embodying circuitry configured to enable communication between the controller and an external device, first I/O pads disposed on the first IC die, second I/O pads disposed on the second IC die, wire bonding interconnections coupling at least one of the first I/O pads with at least one of the second I/O pads, and a memory array formed on a third IC die and configured to enable communication with the controller. In a second embodiment the memory array is alternatively integrated into the first IC die. | 04-02-2009 |
| 20090089481 | Leveraging Portable System Power to Enhance Memory Management and Enable Application Level Features - A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window. Additionally, in a data write operations, where the memory device receives data from a host, stores the data in volatile memory, and then writes the data into the non-volatile memory, the memory device sends the host an acknowledgment of the data having been written into the non-volatile memory after it has been store in the volatile memory, but before the write into the non-volatile memory is complete. | 04-02-2009 |
| 20090210637 | PROVIDING DEVICE PARAMETERS - A non-volatile storage device has first and second controllers that provide external access to non-volatile memory using different protocols. In response to a request from the first controller, the second controller retrieves parameters from the non-volatile memory and provides the retrieved parameters to the first controller. In one embodiment, the device parameters are USB descriptors, which may include a vendor ID, a product ID, a product string, and/or a serial number. The first controller may be a Universal Serial Bus (USB) card reader controller. Examples of the second controller include a Secure Digital (SD) controller, a CompactFlash (CF) controller, a MemoryStick controller, or a different type of controller that is able to provide external access to the non-volatile memory. The first controller provides the device parameters to a host during enumeration of the non-volatile storage device. The device parameters may be used to establish settings for the first controller. | 08-20-2009 |
| 20090307389 | SWITCHABLE ACCESS STATES FOR NON-VOLATILE STORAGE DEVICES - Techniques for switching access states for accessing non-volatile are disclosed. A plurality of non-volatile memory portions can be effectively presented as: (a) a single logical unit in a first access state (“single unit access state”) and (b) as multiple logical units in a second access state (“multi-unit access state”). An access switching system can be provided for a device that includes a plurality of non-volatile storage portions. As a result, the device can be operable to effectively switch between the first and second access states. In the first access state, the plurality of non-volatile storage portions can be effectively presented as a single logical unit for access by another device, thereby allowing the other device to effectively access the plurality of non-volatile storage portions from a single access point. However, the device can also be operable to switch to a second access state in which the plurality of the non-volatile storage portions can be effectively presented to the other device as multiple logical units, thereby allowing the other device to access the plurality of non-volatile storage portions individually by using multiple access points respectively associated with the multiple logical units presented to the other device. | 12-10-2009 |
| 20100161927 | Method for Using a CAPTCHA Challenge to Protect a Removable Mobile Flash Memory Storage Device - The embodiments described herein generally use a challenge to protect a removable mobile flash memory storage device, where the challenge may be in the form of a “Completely Automated Public Turing Test to Tell Computers and Humans Apart” (“CAPTCHA”). In one embodiment, a method is provided in which a removable mobile flash memory storage device receives a command from a host device, generates a CAPTCHA challenge, provides the CAPTCHA challenge to the host device, receives a response to the CAPTCHA challenge from the host device, determines if the response satisfies the CAPTCHA challenge, and performs the command only if the response satisfies the CAPTCHA challenge. In another embodiment, a removable mobile flash memory storage device is provided for performing these acts. | 06-24-2010 |
