| Patent application number | Description | Published |
|---|
| 20080299904 | WIRELESS COMMUNICATION SYSTEM - A wireless communication system comprises a first communication module including a transmitter configured to generate a modulated magnetic field and a second communication module including a receiver. The receiver of the second communication module includes a solid magnetic field sensor configured to sense the magnetic field. Information is transferred from the first communication module to the second communication module via the magnetic field. | 12-04-2008 |
| 20090262638 | SPIN-TORQUE MEMORY WITH UNIDIRECTIONAL WRITE SCHEME - Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme. | 10-22-2009 |
| 20090268352 | ST-RAM MAGNETIC ELEMENT CONFIGURATIONS TO REDUCE SWITCHING CURRENT - In order to increase an efficiency of spin transfer and thereby reduce the required switching current, a current perpendicular to plane (CPP) magnetic element for a memory device includes either one or both of a free magnetic layer, which has an electronically reflective surface, and a permanent magnet layer, which has perpendicular anisotropy to bias the free magnetic layer. | 10-29-2009 |
| 20100006813 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - A programmable metallization memory cell that has an apertured insulating layer comprising at least one aperture therethrough positioned between the active electrode and the inert electrode. Superionic clusters are present within the at least one aperture, and may extend past the at least one aperture. Also, methods for making a programmable metallization memory cell are disclosed. | 01-14-2010 |
| 20100067281 | VARIABLE WRITE AND READ METHODS FOR RESISTIVE RANDOM ACCESS MEMORY - Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell. | 03-18-2010 |
| 20100075599 | Data Transmission and Exchange Using Spin Waves - Devices are proposed for use in nanoscale data transfer and exchange between electronic components. Spin wave generators translate an input signal charge-carrier based signal to spin waves within a ferromagnetic stripe. The spin waves propagate along the ferromagnetic stripe and are detected by spin wave detectors. Further, signal transfer devices such as a splitter, mixer, and switch are disclosed. Embodiments of the invention provide a solution for replacing copper connections, which is a limiting factor in current and future development of high-performance chips. | 03-25-2010 |
| 20100078741 | STRAM WITH COMPENSATION ELEMENT - Spin-transfer torque memory having a compensation element is disclosed. The spin-transfer torque memory unit includes a synthetic antiferromagnetic reference element, a synthetic antiferromagnetic compensation element, a free magnetic layer between the synthetic antiferromagnetic reference element and the synthetic antiferromagnetic compensation element, and an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the synthetic antiferromagnetic reference element. The free magnetic layer has a saturation moment value greater than 1100 emu/cc. | 04-01-2010 |
| 20100078743 | STRAM WITH ELECTRONICALLY REFLECTIVE INSULATIVE SPACER - Spin-transfer torque memory having a specular insulative spacer is disclosed. The spin-transfer torque memory unit includes a free magnetic layer, a reference magnetic layer, an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the reference magnetic layer, an electrode layer, and an electrically insulating and electronically reflective layer separating the electrode layer and the free magnetic layer. | 04-01-2010 |
| 20100091563 | MAGNETIC MEMORY WITH PHONON GLASS ELECTRON CRYSTAL MATERIAL - A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron crystal layer also be disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element to provide a Peltier effect on the free magnetic element and the reference magnetic element. | 04-15-2010 |
| 20100109108 | STRAM WITH COMPOSITE FREE MAGNETIC ELEMENT - Spin-transfer torque memory includes a composite free magnetic element, a reference magnetic element having a magnetization orientation that is pinned in a reference direction, and an electrically insulating and non-magnetic tunneling barrier layer separating the composite free magnetic element from the magnetic reference element. The free magnetic element includes a hard magnetic layer exchanged coupled to a soft magnetic layer. The composite free magnetic element has a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit. | 05-06-2010 |
| 20100109110 | ST-RAM Cells with Perpendicular Anisotropy - Magnetic spin-torque memory cells, often referred to as magnetic tunnel junction cells, which have magnetic anisotropies (i.e., magnetization orientation at zero field and zero current) of the associated ferromagnetic layers aligned perpendicular to the wafer plane, or “out-of-plane”. A memory cell may have a ferromagnetic free layer, a first pinned reference layer and a second pinned reference layer, each having a magnetic anisotropy perpendicular to the substrate. The free layer has a magnetization orientation perpendicular to the substrate that is switchable by spin torque from a first orientation to an opposite second orientation. | 05-06-2010 |
| 20100128520 | NON VOLATILE MEMORY INCLUDING STABILIZING STRUCTURES - An apparatus that includes a magnetic structure including a reference layer; and a free layer; an exchange coupling spacer layer; and a stabilizing layer, wherein the exchange coupling spacer layer is between the magnetic structure and the stabilizing layer and exchange couples the free layer of the magnetic structure to the stabilizing layer. | 05-27-2010 |
| 20100135067 | NON-VOLATILE MEMORY WITH STRAY MAGNETIC FIELD COMPENSATION - A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure. | 06-03-2010 |
| 20100193758 | PROGRAMMABLE METALLIZATION MEMORY CELL WITH PLANARIZED SILVER ELECTRODE - Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact. | 08-05-2010 |
| 20100197104 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Methods for making a programmable metallization memory cell are disclosed. | 08-05-2010 |
| 20100220512 | PROGRAMMABLE POWER SOURCE USING ARRAY OF RESISTIVE SENSE MEMORY CELLS - Various embodiments of the present invention are generally directed to an apparatus comprising a programmable power source which uses an array of resistive sense memory cells, such as but not limited to STRAM or RRAM cells, to provide a controlled power bias to a load, such as but not limited to a micro-oscillator. In some embodiments, the programmable power source incorporates an array of serially connected resistive sense memory cells. A selectively controllable power level is applied by the programmable power source to a load in relation to a control input which selectively programs at least selected ones of the memory cells to a selected resistance state. | 09-02-2010 |
| 20100238712 | VARIABLE WRITE AND READ METHODS FOR RESISTIVE RANDOM ACCESS MEMORY - Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell. | 09-23-2010 |
| 20100246245 | SPIN-TORQUE MEMORY WITH UNIDIRECTIONAL WRITE SCHEME - Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme. | 09-30-2010 |
| 20100254174 | Resistive Sense Memory with Complementary Programmable Recording Layers - A resistive sense memory and method of writing data thereto. In accordance with various embodiments, the resistive sense memory comprises a first reference layer with a fixed magnetic orientation in a selected direction coupled to a first tunneling barrier, a second reference layer with a fixed magnetic orientation in the selected direction coupled to a second tunneling barrier, and a recording structure disposed between the first and second tunneling barriers comprising first and second free layers. A selected logic state is written to the resistive sense memory by applying a programming input to impart complementary first and second programmed magnetic orientations to the respective first and second free layers. | 10-07-2010 |
| 20110019465 | MAGNETIC TUNNEL JUNCTION WITH COMPENSATION ELEMENT - A magnetic tunnel junction having a compensation element is disclosed. The magnetic tunnel junction includes a synthetic antiferromagnetic reference element, and a synthetic antiferromagnetic compensation element having an opposite magnetization moment to a magnetization moment of the synthetic antiferromagnetic reference element. A free magnetic layer is between the synthetic antiferromagnetic reference element and the synthetic antiferromagnetic compensation element, and an electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic layer from the synthetic antiferromagnetic reference element. The free magnetic layer includes Co | 01-27-2011 |
| 20110049658 | MAGNETIC TUNNEL JUNCTION WITH ELECTRONICALLY REFLECTIVE INSULATIVE SPACER - Magnetic tunnel junctions having a specular insulative spacer are disclosed. The magnetic tunnel junction includes a free magnetic layer, a reference magnetic layer, an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the reference magnetic layer, and an electrically insulating and electronically reflective layer positioned to reflect at least a portion of electrons back into the free magnetic layer. | 03-03-2011 |
| 20110134682 | VARIABLE WRITE AND READ METHODS FOR RESISTIVE RANDOM ACCESS MEMORY - Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell. | 06-09-2011 |
