Patent application number | Description | Published |
20080251932 | Method of forming through-silicon vias with stress buffer collars and resulting devices - A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed. | 10-16-2008 |
20080265391 | ETCHED INTERPOSER FOR INTEGRATED CIRCUIT DEVICES - In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer | 10-30-2008 |
20080303159 | Thin Silicon based substrate - Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die. | 12-11-2008 |
20090072013 | NANO-SCALE PARTICLE PASTE FOR WIRING MICROELECTRONIC DEVICES USING INK-JET PRINTING - Nano-scale particle paste may be used for on-die routing and other applications using deposition and inkjet printing. A metal paste is applied to a surface of a die to electrically couple two spaced apart connection points of the die. Alternatively, or in addition, the paste may contain carbon nanotubes. The paste may be used on other surfaces as well. | 03-19-2009 |
20100193952 | Integrated circuit die containing particale-filled through-silicon metal vias with reduced thermal expansion - A method, apparatus and system with an electrically conductive through hole via of a composite material with a matrix forming a continuous phase and embedded particles, with a different material property than the matrix, forming a dispersed phase, the resulting composite material having a different material property than the matrix. | 08-05-2010 |
20110103438 | FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered. | 05-05-2011 |
20120289002 | FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered. | 11-15-2012 |
20130122656 | FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered. | 05-16-2013 |