Patent application number | Description | Published |
20080203447 | LOW-TEMPERATURE ELECTRICALLY ACTIVATED GATE ELECTRODE AND METHOD OF FABRICATING SAME - A gate electrode structure is provided, which includes, from bottom to top, an optional, yet preferred metallic layer, a Ge rich-containing layer and a Si rich-containing layer. The sidewalls of the Ge rich-containing layer include a surface passivation layer. The inventive gate electrode structure serves as a low-temperature electrically activated gate electrode of a MOSFET in which the materials thereof as well as the method of fabricating the same are compatible with existing MOSFET fabrication techniques. The inventive gate electrode structure is electrically activated at low processing temperatures (on the order of less than 750° C.). Additionally, the inventive gate electrode structure also minimizes gate-depletion effects, does not contaminate a standard MOS fabrication facility and has sufficiently low reactivity of the exposed surfaces that renders such a gate electrode structure compatible with conventional MOSFET processing steps. | 08-28-2008 |
20080217697 | CONTROL OF POLY-Si DEPLETION IN CMOS VIA GAS PHASE DOPING - A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein. | 09-11-2008 |
20080246019 | DEFECT REDUCTION BY OXIDATION OF SILICON - A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation. | 10-09-2008 |
20080254594 | STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS - Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si. | 10-16-2008 |
20080258220 | ION IMPLANTATION COMBINED WITH IN SITU OR EX SITU HEAT TREATMENT FOR IMPROVED FIELD EFFECT TRANSISTORS - This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants. | 10-23-2008 |
20080277690 | STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER - A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations. | 11-13-2008 |
20080280416 | Techniques for Layer Transfer Processing - Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein. In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a three dimensional integrated structure is provided. | 11-13-2008 |
20080296622 | BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS - A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor. | 12-04-2008 |
20090067463 | STRUCTURES HAVING LATTICE-MISMATCHED SINGLE-CRYSTALLINE SEMICONDUCTOR LAYERS ON THE SAME LITHOGRAPHIC LEVEL AND METHODS OF MANUFACTURING THE SAME - A semiconductor substrate containing a single crystalline group IV semiconductor is provided. A single crystalline lattice mismatched group IV semiconductor alloy layer is epitaxially grown on a portion of the semiconductor layer, while another portion of the semiconductor layer is masked. The composition of the lattice mismatched group IV semiconductor alloy layer is tuned to substantially match the lattice constant of a single crystalline compound semiconductor layer, which is subsequently epitaxially grown on the single crystalline lattice mismatched group IV semiconductor alloy layer. Thus, a structure having both the group IV semiconductor layer and the single crystalline compound semiconductor layer is provided on the same semiconductor substrate. Group IV semiconductor devices, such as silicon devices, and compound semiconductor devices, such as GaAs devices having a laser emitting capability, may be formed on the on the same lithographic level of the semiconductor substrate. | 03-12-2009 |
20090092810 | FABRICATION OF SOI WITH GETTERING LAYER - An SOI substrate has a gettering layer of silicon-germanium (SiGe) with 5-10% Ge, and a thickness of approximately 50-1000 nm. Carbon (C) may be added to SiGe to stabilize the dislocation network. The SOI substrate may be a SIMOX SOI substrate, or a bonded SOI substrate, or a seeded SOI substrate. The gettering layer may disposed under a buried oxide (BOX) layer. The gettering layer may be disposed on a backside of the substrate. | 04-09-2009 |
20090117720 | STRAINED SEMICONDUCTOR-ON-INSULATOR BY Si:C COMBINED WITH POROUS PROCESS - A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer. | 05-07-2009 |
20090134460 | STRAINED SEMICONDUCTOR-ON-INSULATOR (sSOI) BY A SIMOX METHOD - A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer. | 05-28-2009 |
20090186455 | DISPOSABLE METALLIC OR SEMICONDUCTOR GATE SPACER - A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as a metal, a metal nitride, or a semiconductor material having high reactivity with oxygen. The disposable gate spacer absorbs any oxygen during subsequent high temperature processing such as a stress memorization anneal. A metal is deposited over, and reacted with, the gate electrode and source and drain regions to form metal semiconductor alloy regions. The disposable gate spacer is subsequently removed selective to the metal semiconductor alloy regions. A porous or non-porous low-k dielectric material is deposited to provide a low parasitic capacitance between the gate electrode and the source and drain regions. The gate dielectric maintains the original dielectric constant since the disposable gate spacer prevents absorption of additional oxygen during high temperature processes. | 07-23-2009 |
20090217967 | POROUS SILICON QUANTUM DOT PHOTODETECTOR - Embodiments of the present invention provide a solar energy converter, which includes a silicon layer having at least two regions of a first and a second conductivity type that form a P-N junction, at least a portion of the silicon layer being porous, and pores in the portion of porous silicon containing a semiconductor material, the semiconductor material being different from silicon; and a first and a second electrode being placed at a bottom and a top surface of the silicon layer respectively. Methods of manufacturing the same are also provided. | 09-03-2009 |
20090233079 | Techniques for Layer Transfer Processing - Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein. In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a three dimensional integrated structure is provided. | 09-17-2009 |
20090298258 | QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE - The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition. | 12-03-2009 |
20090298269 | STRUCTURES HAVING LATTICE-MISMATCHED SINGLE-CRYSTALLINE SEMICONDUCTOR LAYERS ON THE SAME LITHOGRAPHIC LEVEL AND METHODS OF MANUFACTURING THE SAME - A semiconductor substrate containing a single crystalline group IV semiconductor is provided. A single crystalline lattice mismatched group IV semiconductor alloy layer is epitaxially grown on a portion of the semiconductor layer, while another portion of the semiconductor layer is masked. The composition of the lattice mismatched group IV semiconductor alloy layer is tuned to substantially match the lattice constant of a single crystalline compound semiconductor layer, which is subsequently epitaxially grown on the single crystalline lattice mismatched group IV semiconductor alloy layer. Thus, a structure having both the group IV semiconductor layer and the single crystalline compound semiconductor layer is provided on the same semiconductor substrate. Group IV semiconductor devices, such as silicon devices, and compound semiconductor devices, such as GaAs devices having a laser emitting capability, may be formed on the on the same lithographic level of the semiconductor substrate. | 12-03-2009 |
20090302353 | STRUCTURES CONTAINING ELECTRODEPOSITED GERMANIUM AND METHODS FOR THEIR FABRICATION - Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits. | 12-10-2009 |
20100032684 | ION IMPLANTATION FOR SUPPRESSION OF DEFECTS IN ANNEALED SiGe LAYERS - A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided. | 02-11-2010 |
20100035409 | CRYSTALLINE SILICON SUBSTRATES WITH IMPROVED MINORITY CARRIER LIFETIME - A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200° C. or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl. | 02-11-2010 |
20100112792 | THICK EPITAXIAL SILICON BY GRAIN REORIENTATION ANNEALING AND APPLICATIONS THEREOF - The invention provides a high temperature (about 1150° C. or greater) annealing process for converting thick polycrystalline Si layers on the order of 1 μm to 40 μm on a single crystal seed layer into thick single crystal Si layers having the orientation of the seed layer, thus allowing production of thick Si films having the quality of single crystal silicon at high rates and low cost of processing. Methods of integrating such high temperature processing into solar cell fabrication are described, with particular attention to process flows in which the seed layer is disposed on a porous silicon release layer. Another aspect pertains to the use of similar high temperature anneals for poly-Si grain growth and grain boundary passivation. A further aspect relates to structures in which these thick single crystal Si films and passivated poly-Si films are incorporated. | 05-06-2010 |
20100123205 | METHOD TO PREVENT SURFACE DECOMPOSITION OF III-V COMPOUND SEMICONDUCTORS - A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor. | 05-20-2010 |
20100176495 | LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS - A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive layer formed on the lower insulating layer; an upper insulating layer formed on the electrically conductive layer, the upper insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; and a semiconductor layer formed on the upper insulating layer. | 07-15-2010 |
20100197118 | MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES - A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices. | 08-05-2010 |
20100261319 | N-type carrier enhancement in semiconductors - A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage. Repeating the implantation and the thermal annealing until the target n-type carrier concentration has been reached. | 10-14-2010 |
20110212622 | SURFACE TEXTURING USING A LOW QUALITY DIELECTRIC LAYER - A low cost method is described for forming a textured Si surface such as for a solar cell which includes forming a dielectric layer containing pinholes, anisotropically etching through the pinholes to form inverted pyramids in the Si surface and removing the dielectric layer thereby producing a high light trapping efficiency for incident radiation. | 09-01-2011 |
20110230030 | STRAIN-PRESERVING ION IMPLANTATION METHODS - An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized. | 09-22-2011 |
20110263104 | THIN BODY SEMICONDUCTOR DEVICES - A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented. | 10-27-2011 |
20110272010 | HIGH WORK FUNCTION METAL INTERFACIAL FILMS FOR IMPROVING FILL FACTOR IN SOLAR CELLS - A photovoltaic device and method include a doped transparent electrode, and a light-absorbing semiconductor structure including a first semiconductor layer. An ultra-thin layer of a non-transparent metal is formed between the transparent electrode and the first semiconductor layer to form a reduced barrier contact wherein the ultra-thin layer is light transmissive. When the ultrathin metal forms discrete individual dots, it permits a plasmonic light trapping effect to increase the current at solar cells. | 11-10-2011 |
20110278172 | ELECTRODEPOSITION UNDER ILLUMINATION WITHOUT ELECTRICAL CONTACTS - A method of forming patterned metallization by electrodeposition under illumination without external voltage supply on a photovoltaic structure or on n-type region of a transistor/junction. | 11-17-2011 |
20120003819 | Methods and apparatus for selective epitaxy of si-containing materials and substitutionally doped crystalline si-containing material - The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550° C. and a pressure in the range of about 10 mTorr-200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions. | 01-05-2012 |
20120009766 | STRAINED SEMICONDUCTOR-ON-INSULATOR BY ADDITION AND REMOVAL OF ATOMS IN A SEMICONDUCTOR-ON-INSULATOR - A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate. | 01-12-2012 |
20120012167 | SOLAR CELL EMPLOYING AN ENHANCED FREE HOLE DENSITY P-DOPED MATERIAL AND METHODS FOR FORMING THE SAME - A p-doped semiconductor layer of a photovoltaic device is formed employing an inert gas within a carrier gas. The presence of the inert gas within the carrier gas increases free hole density within the p-doped semiconductor layer. This decreases the Schottky barrier at an interface with a transparent conductive material layer, thereby significantly reducing the series resistance of the photovoltaic device. The reduction of the series resistance increases the open-circuit voltage, the fill factor, and the efficiency of the photovoltaic device. This effect is more prominent if the p-doped semiconductor layer is also doped with carbon, and has a band gap greater than 1.85V. The p-doped semiconductor material of the p-doped semiconductor layer can be hydrogenated if the carrier gas includes a mix of H | 01-19-2012 |
20120031454 | EFFICIENT NANOSCALE SOLAR CELL AND FABRICATION METHOD - A photovoltaic device and method include a substrate layer having a plurality of structures including peaks and troughs formed therein. A continuous photovoltaic stack is conformally formed over the substrate layer and extends over the peaks and troughs. The photovoltaic stack has a thickness of less than one micron and is configured to transduce incident radiation into current flow. | 02-09-2012 |
20120031476 | COMPOSITIONALLY-GRADED BAND GAP HETEROJUNCTION SOLAR CELL - A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device. | 02-09-2012 |
20120031477 | PHOTOVOLTAIC DEVICES WITH AN INTERFACIAL BAND-GAP MODIFYING STRUCTURE AND METHODS FOR FORMING THE SAME - A Schottky-barrier-reducing layer is provided between a p-doped semiconductor layer and a transparent conductive material layer of a photovoltaic device. The Schottky-barrier-reducing layer can be a conductive material layer having a work function that is greater than the work function of the transparent conductive material layer. The conductive material layer can be a carbon-material layer such as a carbon nanotube layer or a graphene layer. Alternately, the conductive material layer can be another transparent conductive material layer having a greater work function than the transparent conductive material layer. The reduction of the Schottky barrier reduces the contact resistance across the transparent material layer and the p-doped semiconductor layer, thereby reducing the series resistance and increasing the efficiency of the photovoltaic device. | 02-09-2012 |
20120037998 | CMOS TRANSISTORS WITH STRESSED HIGH MOBILITY CHANNELS - A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively. | 02-16-2012 |
20120060905 | NANOWIRES FORMED BY EMPLOYING SOLDER NANODOTS - A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer. | 03-15-2012 |
20120104390 | Germanium-Containing Release Layer For Transfer of a Silicon Layer to a Substrate - A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed. | 05-03-2012 |
20120112208 | STRESSED TRANSISTOR WITH IMPROVED METASTABILITY - An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material. | 05-10-2012 |
20120118383 | Autonomous Integrated Circuit - An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer. | 05-17-2012 |
20120135587 | N-type carrier enhancement in semiconductors - A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage. Repeating the implantation and the thermal annealing until the target n-type carrier concentration has been reached. | 05-31-2012 |
20120152352 | PHOTOVOLTAIC DEVICES WITH AN INTERFACIAL GERMANIUM-CONTAINING LAYER AND METHODS FOR FORMING THE SAME - A germanium-containing layer is provided between a p-doped silicon-containing layer and a transparent conductive material layer of a photovoltaic device. The germanium-containing layer can be a p-doped silicon-germanium alloy layer or a germanium layer. The germanium-containing layer has a greater atomic concentration of germanium than the p-doped silicon-containing layer. The presence of the germanium-containing layer has the effect of reducing the series resistance and increasing the shunt resistance of the photovoltaic device, thereby increasing the fill factor and the efficiency of the photovoltaic device. In case a silicon-germanium alloy layer is employed, the closed circuit current density also increases. | 06-21-2012 |
20120156393 | Deposition of Hydrogenated Thin Film - A hydrogenated thin film is formed in a controlled vacuum on a substrate by evaporating one or more solid materials and passing the resulting vapor and a hydrogen-containing gas into a space between two electrodes. One of the electrodes includes openings for allowing the vapor to enter the space. Plasma is generated within the space to cause dissociation of the hydrogen-containing gas and promote a reaction between the material(s) and hydrogen-containing gas. | 06-21-2012 |
20120156861 | QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE - Methods for removing or reducing the thickness of a material layer remaining at Si-Si interfaces after silicon wafer bonding. The methods include an anneal which is performed at a temperature sufficient to dissolve oxide, yet not melt silicon. | 06-21-2012 |
20120187539 | DEVICE AND METHOD FOR BORON DIFFUSION IN SEMICONDUCTORS - A device and method for semiconductor fabrication includes forming a buffer layer on a semiconductor substrate and depositing an amorphous elemental layer on the buffer layer. Elements of the elemental layer are diffused through the buffer layer and into the semiconductor layer. | 07-26-2012 |
20120190161 | N-type carrier enhancement in semiconductors - A field effect transistor (FET) has a channel hosted in Ge. The FET has silicon-germanium (SiGe) source and drain formed by selective epitaxy. The SiGe source and drain exert a tensile stress onto the Ge channel. During forming of the SiGe source and drain, an n-type dopant species and a compensating species are being incorporated into the SiGe source and drain. The n-type dopant species and the compensating species are so selected that the size of the SiGe atomic radius is inbetween the dopant atomic radius and the compensating species atomic radius. | 07-26-2012 |
20120190177 | N-type carrier enhancement in semiconductors - A method includes epitaxially growing a germanium (Ge) layer onto a Ge substrate and incorporating a compensating species with a compensating atomic radius into the Ge layer. The method includes implanting an n-type dopant species with a dopant atomic radius into the Ge layer. The method includes selecting the n-type dopant species and the compensating species in such manner that the size of the Ge atomic radius is inbetween the n-type dopant atomic radius and the compensating atomic radius. | 07-26-2012 |
20120192913 | MIXED TEMPERATURE DEPOSITION OF THIN FILM SILICON TANDEM CELLS - Fabrication of a tandem photovoltaic device includes forming a bottom cell having an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. A top cell is formed relative to the bottom cell. The top cell has an N-type layer, a P-type layer and a top intrinsic layer therebetween. The top intrinsic layer is formed of an undoped material deposited at a temperature that is different from the bottom intrinsic layer such that band gap energies for the top intrinsic layer and the bottom intrinsic layer are progressively lower for each cell. | 08-02-2012 |
20120210932 | LOW-TEMPERATURE SELECTIVE EPITAXIAL GROWTH OF SILICON FOR DEVICE INTEGRATION - An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000. | 08-23-2012 |
20120211079 | SILICON PHOTOVOLTAIC ELEMENT AND FABRICATION METHOD - A method of forming a photovoltaic device that includes providing an absorption layer of a first crystalline semiconductor material having a first conductivity type, and epitaxially growing a second crystalline semiconductor layer of a second conductivity type that is opposite the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The temperature of the epitaxially growing the second crystalline semiconductor layer does not exceed 500° C. Contacts are formed in electrical communication with the absorption layer and the second crystalline semiconductor layer. | 08-23-2012 |
20120216862 | Silicon: Hydrogen Photovoltaic Devices, Such As Solar Cells, Having Reduced Light Induced Degradation And Method Of Making Such Devices - A method of producing a photovoltaic device includes providing a stretchable substrate for the photovoltaic device; and stretching the substrate to produce a stretched substrate. The method further includes depositing a structure comprising hydrogenated amorphous silicon onto the stretched substrate; and subjecting the deposited hydrogenated amorphous silicon structure and the stretched substrate to a compressive force to form a compressively strained photovoltaic device. | 08-30-2012 |
20120222730 | TANDEM SOLAR CELL WITH IMPROVED ABSORPTION MATERIAL - A photosensitive device and method includes a top cell having an N-type layer, a P-type layer and a top intrinsic layer therebetween. A bottom cell includes an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. The bottom intrinsic layer includes a Cu—Zn—Sn containing chalcogenide. | 09-06-2012 |
20120252216 | Low-Temperature in-situ Removal of Oxide from a Silicon Surface During CMOS Epitaxial Processing - Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof. | 10-04-2012 |
20120255600 | METHOD OF BONDING AND FORMATION OF BACK SURFACE FIELD (BSF) FOR MULTI-JUNCTION III-V SOLAR CELLS - A photovoltaic device including at least one top cell that include at least one semiconductor material; a bottom cell of a germanium containing material having a thickness of 10 microns or less; and a back surface field (BSF) region provided by a eutectic alloy layer of aluminum and germanium on the back surface of the bottom cell of that is opposite the interface between the bottom cell and at least one of the top cells. The eutectic alloy of aluminum and germanium bonds the bottom cell of the germanium-containing material to a supporting substrate. | 10-11-2012 |
20120285520 | WAFER BONDED SOLAR CELLS AND FABRICATION METHODS - A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch. | 11-15-2012 |
20120295417 | SELECTIVE EPITAXIAL GROWTH BY INCUBATION TIME ENGINEERING - A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed. | 11-22-2012 |
20120295421 | LOW TEMPERATURE SELECTIVE EPITAXY OF SILICON GERMANIUM ALLOYS EMPLOYING CYCLIC DEPOSIT AND ETCH - Cyclic deposit and etch (CDE) selective epitaxial growth employs an etch chemistry employing a combination of hydrogen chloride and a germanium-containing gas to provide selective deposition of a silicon germanium alloy at temperatures lower than 625° C. High strain epitaxial silicon germanium alloys having a germanium concentration greater than 35 atomic percent in a temperature range between 400° C. and 550° C. A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium-containing precursor gas is employed to deposit the silicon germanium alloy with thickness uniformity and at a high deposition rate during each deposition step in this temperature range. Presence of the germanium-containing gas in the etch chemistry enhances the etch rate of the deposited silicon germanium alloy material during the etch step. | 11-22-2012 |
20120305940 | Defect Free Si:C Epitaxial Growth - A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the <100> crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain. | 12-06-2012 |
20120305989 | METHOD TO PREVENT SURFACE DECOMPOSITION OF III-V COMPOUND SEMICONDUCTORS - A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor. | 12-06-2012 |
20120309153 | METHOD TO PREVENT SURFACE DECOMPOSITION OF III-V COMPOUND SEMICONDUCTORS - A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor. | 12-06-2012 |
20120309269 | LOW-TEMPERATURE METHODS FOR SPONTANEOUS MATERIAL SPALLING - Method to (i) introduce additional control into a material spalling process, thus improving both the crack initiation and propagation, and (ii) increase the range of selectable spalling depths are provided. In one embodiment, the method includes providing a stressor layer on a surface of a base substrate at a first temperature which is room temperature. Next, the base substrate including the stressor layer is brought to a second temperature which is less than room temperature. The base substrate is spalled at the second temperature to form a spalled material layer. Thereafter, the spalled material layer is returned to room temperature, i.e., the first temperature. | 12-06-2012 |
20120312361 | EMITTER STRUCTURE AND FABRICATION METHOD FOR SILICON HETEROJUNCTION SOLAR CELL - A method of forming a photovoltaic device that includes providing an absorption layer of a first crystalline semiconductor material having a first conductivity type, epitaxially growing a second crystalline semiconductor layer of a second conductivity type that is opposite the first conductivity type, and growing a doped amorphous or nanocrystalline passivation layer of a second conductivity type that is opposite to the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The temperature of the epitaxially growing the second crystalline semiconductor layer does not exceed 500° C. Contacts are formed in electrical communication with the absorption layer and the second crystalline semiconductor layer. | 12-13-2012 |
20120312362 | SILICON-CONTAINING HETEROJUNCTION PHOTOVOLTAIC ELEMENT AND DEVICE - A photovoltaic device is provided in which the tunneling barrier for hole collection at either the front contact or the back contact of a silicon heterojunction cell is reduced, without compromising the surface passivation either the front contact or at the back contact. This is achieved in the present disclosure by replacing the intrinsic and/or doped hydrogenated amorphous silicon (a-Si:H) layer(s) at the back contact or at the front contact with an intrinsic and/or doped layer(s) of a semiconductor material having a lower valence band-offset than that of a:Si—H with c-Si, and/or a higher activated doping concentration compared to that of doped hydrogenated amorphous Si. The higher level of activated doping is due to the higher doping efficiency of the back contact or front contact semiconductor material compared to that of amorphous Si, and/or modulation doping of the back or front contact semiconducting material. As a result, the tunneling barrier for hole collection is reduced and the cell efficiency is improved accordingly. | 12-13-2012 |
20120318334 | SPALLING METHODS TO FORM MULTI-JUNCTION PHOTOVOLTAIC STRUCTURE - A method cleaving a semiconductor material that includes providing a germanium substrate having a germanium and tin alloy layer is present therein. A stressor layer is deposited on a surface of the germanium substrate. A stress from the stressor layer is applied to the germanium substrate, in which the stress cleaves the germanium substrate to provide a cleaved surface. The cleaved surface of the germanium substrate is then selective to the germanium and tin alloy layer of the germanium substrate. In another embodiment, the germanium and tin alloy layer may function as a fracture plane during a spalling method. | 12-20-2012 |
20120318335 | TANDEM SOLAR CELL WITH IMPROVED TUNNEL JUNCTION - A photovoltaic device and method for fabricating a photovoltaic device include forming a light-absorbing semiconductor structure on a transmissive substrate including a first doped layer and forming an intrinsic layer on the first doped layer, wherein the intrinsic layer includes an amorphous material. The intrinsic layer is treated with a plasma to form seed sites. A first tunnel junction layer is formed on the intrinsic layer by growing microcrystals from the seed sites. | 12-20-2012 |
20120318336 | CONTACT FOR SILICON HETEROJUNCTION SOLAR CELLS - A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion. | 12-20-2012 |
20120318338 | NANOWIRES FORMED BY EMPLOYING SOLDER NANODOTS - A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer. | 12-20-2012 |
20120318339 | SOLAR CELL EMPLOYING AN ENHANCED FREE HOLE DENSITY P-DOPED MATERIAL AND METHODS FOR FORMING THE SAME - A p-doped semiconductor layer of a photovoltaic device is formed employing an inert gas within a carrier gas. The presence of the inert gas within the carrier gas increases free hole density within the p-doped semiconductor layer. This decreases the Schottky barrier at an interface with a transparent conductive material layer, thereby significantly reducing the series resistance of the photovoltaic device. The reduction of the series resistance increases the open-circuit voltage, the fill factor, and the efficiency of the photovoltaic device. This effect is more prominent if the p-doped semiconductor layer is also doped with carbon, and has a band gap greater than 1.85V. The p-doped semiconductor material of the p-doped semiconductor layer can be hydrogenated if the carrier gas includes a mix of H | 12-20-2012 |
20120318342 | UNIFORMLY DISTRIBUTED SELF-ASSEMBLED CONE-SHAPED PILLARS FOR HIGH EFFICIENCY SOLAR CELLS - A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device. | 12-20-2012 |
20120322227 | METHOD FOR CONTROLLED LAYER TRANSFER - A method of controlled layer transfer is provided. The method includes providing a stressor layer to a base substrate. The stressor layer has a stressor layer portion located atop an upper surface of the base substrate and a self-pinning stressor layer portion located adjacent each sidewall edge of the base substrate. A spalling inhibitor is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion. After spalling, the stressor layer portion is removed from atop a spalled portion of the base substrate. | 12-20-2012 |
20120322230 | METHOD FOR FORMING TWO DEVICE WAFERS FROM A SINGLE BASE SUBSTRATE UTILIZING A CONTROLLED SPALLING PROCESS - The present disclosure provides a method for forming two device wafers starting from a single base substrate. The method includes first providing a structure which includes a base substrate with device layers located on, or within, a topmost surface and a bottommost surface of the base substrate. The base substrate may have double side polished surfaces. The structure including the device layers is spalled in a region within the base substrate that is between the device layers. The spalling provides a first device wafer including a portion of the base substrate and one of the device layers, and a second device wafer including another portion of the base substrate and the other of the device layer. | 12-20-2012 |
20120322244 | METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE - A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate. | 12-20-2012 |
20120325304 | CONTACT FOR SILICON HETEROJUNCTION SOLAR CELLS - A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion. | 12-27-2012 |
20120325305 | OHMIC CONTACT BETWEEN THIN FILM SOLAR CELL AND CARBON-BASED TRANSPARENT ELECTRODE - A photovoltaic device and method include a photovoltaic stack having an N-doped layer, a P-doped layer and an intrinsic layer. A transparent electrode is formed on the photovoltaic stack and includes a carbon based layer and a high work function metal layer. The high work function metal layer is disposed at an interface between the carbon based layer and the P-doped layer such that the high work function metal layer forms a reduced barrier contact and is light transmissive. | 12-27-2012 |
20120329197 | METHOD OF BONDING AND FORMATION OF BACK SURFACE FIELD (BSF) FOR MULTI-JUNCTION III-V SOLAR CELLS - A photovoltaic device including at least one top cell that include at least one III-V semiconductor material; a bottom cell of a germanium containing material having a thickness of | 12-27-2012 |
20120329206 | SILICON-CONTAINING HETEROJUNCTION PHOTOVOLTAIC ELEMENT AND DEVICE - In one embodiment, a method of forming a photovoltaic device is provided which includes providing an absorption layer comprising a silicon-containing semiconductor layer of a first conductivity type and having a top surface and a bottom surface that opposes the top surface. A front contact is formed on the top surface of the absorption layer, and a back contact is formed on the bottom surface of the absorption layer. The forming of the front contact and the back contact can occur in any order. The back contact that is formed comprises at least one back contact semiconductor material layer of the first conductivity type and having a lower band-offset than that of hydrogenated amorphous silicon with crystalline Si and/or a higher activated doping of the first conductivity type than that of the doped hydrogenated amorphous silicon layer. | 12-27-2012 |
20130000704 | THREE-DIMENSIONAL CONDUCTIVE ELECTRODE FOR SOLAR CELL - A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack. | 01-03-2013 |
20130000706 | TANDEM SOLAR CELL WITH IMPROVED TUNNEL JUNCTION - A photovoltaic device and method for fabricating a photovoltaic device include forming a light-absorbing semiconductor structure on a transmissive substrate including a first doped layer and forming an intrinsic layer on the first doped layer, wherein the intrinsic layer includes an amorphous material. The intrinsic layer is treated with a plasma to form seed sites. A first tunnel junction layer is formed on the intrinsic layer by growing microcrystals from the seed sites. | 01-03-2013 |
20130001657 | SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT - A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed. | 01-03-2013 |
20130001659 | SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT - A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed. | 01-03-2013 |
20130005116 | EDGE-EXCLUSION SPALLING METHOD FOR IMPROVING SUBSTRATE REUSABILITY - A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region where the stressor layer is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In one embodiment, the method includes forming an edge exclusion material on an upper surface and near an edge of a base substrate. A stressor layer is then formed on exposed portions of the upper surface of the base substrate and atop the edge exclusion material, A portion of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled. | 01-03-2013 |
20130005119 | METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE - A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate. | 01-03-2013 |
20130014811 | HETEROJUNCTION III-V SOLAR CELL PERFORMANCEAANM Bedell; Stephen W.AACI Wappingers FallsAAST NYAACO USAAGP Bedell; Stephen W. Wappingers Falls NY USAANM Hekmatshoartabari; BahmanAACI Mount KiscoAAST NYAACO USAAGP Hekmatshoartabari; Bahman Mount Kisco NY USAANM Sadana; Devendra K.AACI PleasantvilleAAST NYAACO USAAGP Sadana; Devendra K. Pleasantville NY USAANM Shahidi; Ghavam G.AACI Pound RidgeAAST NYAACO USAAGP Shahidi; Ghavam G. Pound Ridge NY USAANM Shahrjerdi; DavoodAACI OssiningAAST NYAACO USAAGP Shahrjerdi; Davood Ossining NY US | 01-17-2013 |
20130019929 | REDUCTION OF LIGHT INDUCED DEGRADATION BY MINIMIZING BAND OFFSET - A device and method for reducing degradation in a photovoltaic device includes adjusting a band offset of the device during one or more of forming an electrode, forming a first doped layer or forming an intrinsic layer. The adjusting reduces a band offset between one or more of the electrode, the first doped layer and the intrinsic layer to reduce light-induced degradation of the device. A second doped layer is formed on the intrinsic layer. | 01-24-2013 |
20130019944 | METHOD OF STABILIZING HYDROGENATED AMORPHOUS SILICON AND AMORPHOUS HYDROGENATED SILICON ALLOYS - A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material. | 01-24-2013 |
20130019945 | METHOD OF STABILIZING HYDROGENATED AMORPHOUS SILICON AND AMORPHOUS HYDROGENATED SILICON ALLOYS - A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material. | 01-24-2013 |
20130025653 | III-V PHOTOVOLTAIC ELEMENTS - Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of Si | 01-31-2013 |
20130025654 | MULTI-JUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A method of forming a photovoltaic device that includes bonding a substrate to a germanium-containing semiconductor layer with a stressor layer, wherein the stressor layer cleaves the germanium-containing semiconductor layer. At least one semiconductor layer is formed on a cleaved surface of the germanium-containing semiconductor layer that is opposite the conductivity type of the germanium-containing semiconductor layer to provide a first solar cell. The first solar cell absorbs a first range of wavelengths. At least one second solar cell may be formed on the first solar cell, wherein the at least one second solar cell is composed of at least one semiconductor material to absorb a second range of wavelengths that is different than the first range wavelengths absorbed by the first solar cell. | 01-31-2013 |
20130025655 | HETEROJUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate. | 01-31-2013 |
20130025658 | HETEROJUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate. | 01-31-2013 |
20130025659 | MULTI-JUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A method of forming a photovoltaic device that includes bonding a substrate to a germanium-containing semiconductor layer with a stressor layer, wherein the stressor layer cleaves the germanium-containing semiconductor layer. At least one semiconductor layer is formed on a cleaved surface of the germanium-containing semiconductor layer that is opposite the conductivity type of the germanium-containing semiconductor layer to provide a first solar cell. The first solar cell absorbs a first range of wavelengths. At least one second solar cell may be formed on the first solar cell, wherein the at least one second solar cell is composed of at least one semiconductor material to absorb a second range of wavelengths that is different than the first range wavelengths absorbed by the first solar cell. | 01-31-2013 |
20130040438 | EPITAXIAL PROCESS WITH SURFACE CLEANING FIRST USING HCl/GeH4/H2SiCl2 - A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH | 02-14-2013 |
20130040440 | EPITAXIAL PROCESS WITH SURFACE CLEANING FIRST USING HCl/GeH4/H2SiCl2 - A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH | 02-14-2013 |
20130048061 | MONOLITHIC MULTI-JUNCTION PHOTOVOLTAIC CELL AND METHOD - A device and method for fabrication of a multi-junction photovoltaic device includes providing a parent substrate including a single crystal III-V material. The parent substrate forms a III-V cell of the multi-junction photovoltaic device. A lattice-matched Germanium layer is epitaxially grown on the III-V material to form a final cell of the multi-junction photovoltaic device. The Germanium layer is bonded to a foreign substrate. | 02-28-2013 |
20130049150 | FORMATION OF METAL NANOSPHERES AND MICROSPHERES - Hemispheres and spheres are formed and employed for a plurality of applications. Hemispheres are employed to form a substrate having an upper surface and a lower surface. The upper surface includes peaks of pillars which have a base attached to the lower surface. The peaks have a density defined at the upper surface by an array of hemispherical metal structures that act as a mask during an etch to remove substrate material down to the lower surface during formation of the pillars. The pillars are dense and uniform and include a microscale average diameter. The spheres are formed as independent metal spheres or nanoparticles for other applications. | 02-28-2013 |
20130082357 | PREFORMED TEXTURED SEMICONDUCTOR LAYER - A base layer of a semiconductor material is formed with a naturally textured surface. The base layer may be incorporated within a photovoltaic structure. A controlled spalling technique, in which substrate fracture is propagated in a selected direction to cause the formation of facets, is employed. Spalling in the [110] directions of a (001) silicon substrate results in the formation of such facets of the resulting base layer, providing a natural surface texture. | 04-04-2013 |
20130092213 | EFFICIENCY RESTORATION IN A PHOTOVOLTAIC CELL - The electrical output efficiency of a photovoltaic thermal system can be restored from degradation due to light exposure by annealing a photovoltaic thermal cell at an elevated temperature. The elevated temperature at the photovoltaic thermal cell can be provided by redirecting the flow of a heat exchange fluid to bypass a heat exchanger unit. A boiler unit may be employed to provide additional heating of the heat exchange fluid during the anneal. Further, a variable configuration lid can be provided over a front surface of the photovoltaic thermal cell to control ventilation over the front surface. During the anneal, the position of the variable configuration lid can be set so as to trap heat above the front surface and to elevate the anneal temperature further. | 04-18-2013 |
20130092214 | EFFICIENCY RESTORATION IN A PHOTOVOLTAIC CELL - The electrical output efficiency of a photovoltaic thermal system can be restored from degradation due to light exposure by annealing a photovoltaic thermal cell at an elevated temperature. The elevated temperature at the photovoltaic thermal cell can be provided by redirecting the flow of a heat exchange fluid to bypass a heat exchanger unit. A boiler unit may be employed to provide additional heating of the heat exchange fluid during the anneal. Further, a variable configuration lid can be provided over a front surface of the photovoltaic thermal cell to control ventilation over the front surface. During the anneal, the position of the variable configuration lid can be set so as to trap heat above the front surface and to elevate the anneal temperature further. | 04-18-2013 |
20130092218 | BACK-SURFACE FIELD STRUCTURES FOR MULTI-JUNCTION III-V PHOTOVOLTAIC DEVICES - A multi-junction III-V photovoltaic device is provided that includes at least one top cell comprised of at least one III-V compound semiconductor material; and a bottom cell in contact with a surface of the at least one top cell. The bottom cell includes a germanium-containing layer in contact with the at least one top cell, at least one intrinsic hydrogenated silicon-containing layer in contact with a surface of the germanium-containing layer, and at least one doped hydrogenated silicon-containing layer in contact with a surface of the at least one intrinsic hydrogenated silicon-containing layer. The intrinsic and doped silicon-containing layers can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline. | 04-18-2013 |
20130095598 | BACK-SURFACE FIELD STRUCTURES FOR MULTI-JUNCTION III-V PHOTOVOLTAIC DEVICES - A multi-junction III-V photovoltaic device is provided that includes at least one top cell comprised of at least one III-V compound semiconductor material; and a bottom cell in contact with a surface of the at least one top cell. The bottom cell includes a germanium-containing layer in contact with the at least one top cell, at least one intrinsic hydrogenated silicon-containing layer in contact with a surface of the germanium-containing layer, and at least one doped hydrogenated silicon-containing layer in contact with a surface of the at least one intrinsic hydrogenated silicon-containing layer. The intrinsic and doped silicon-containing layers can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline. | 04-18-2013 |
20130095599 | PHOTOVOLTAIC DEVICE USING NANO-SPHERES FOR TEXTURED ELECTRODES - An electronic device includes a substrate and a plurality of particles anchored to the substrate. An electrode material is formed over the particles and configured to form peaks over the particles. One or more operational layers are fog led over the electrode material for performing a device function. | 04-18-2013 |
20130099318 | THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS - A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate. | 04-25-2013 |
20130099319 | THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS - A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate. | 04-25-2013 |
20130112275 | SILICON HETEROJUNCTION PHOTOVOLTAIC DEVICE WITH WIDE BAND GAP EMITTER - A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm. | 05-09-2013 |
20130118565 | TEMPERATURE GRADING FOR BAND GAP ENGINEERING OF PHOTOVOLTAIC DEVICES - A method for fabricating a photovoltaic device includes depositing a p-type layer at a first temperature and depositing an intrinsic layer while gradually increasing a deposition temperature to a final temperature. The intrinsic layer deposition is completed at the final temperature. An n-type layer is formed on the intrinsic layer. | 05-16-2013 |
20130126493 | SPALLING WITH LASER-DEFINED SPALL EDGE REGIONS - Laser ablation can be used to form a trench within at least a blanket layer of a stressor layer that is atop a base substrate. A non-ablated portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can also be used to form a trench within a blanket material stack including at least a plating seed layer. A stressor layer is formed on the non-ablated portions of the material stack and one portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can be further used to form a trench that extends through a blanket stressor layer and into the base substrate itself. The trench has an edge that defines the edge of the material layer region to be spalled. | 05-23-2013 |
20130126890 | INTEGRATING ACTIVE MATRIX INORGANIC LIGHT EMITTING DIODES FOR DISPLAY DEVICES - A method of forming an active matrix, light emitting diode (LED) array includes removing, from a base substrate, a layer of inorganic LED material originally grown thereupon; and bonding the removed layer of inorganic LED material to an active matrix, thin film transistor (TFT) backplane array. | 05-23-2013 |
20130134444 | STRESSED TRANSISTOR WITH IMPROVED METASTABILITY - An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material. | 05-30-2013 |
20130180564 | FIELD-EFFECT PHOTOVOLTAIC ELEMENTS - Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering. | 07-18-2013 |
20130193441 | Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer - Improved semiconductor substrates are provided that employ a wide bandgap material between the channel and the insulator. A semiconductor substrate comprises a channel layer comprised of a III-V material; an insulator layer; and a wide bandgap material between the channel layer and the insulator layer, wherein a conduction band offset (ΔE | 08-01-2013 |
20130193482 | Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets - Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔE | 08-01-2013 |
20130193483 | Mosfet Structures Having Compressively Strained Silicon Channel - MOSFET structures are provided having a compressively strained silicon channel. A semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel. | 08-01-2013 |
20130196486 | Semiconductor Substrates Using Bandgap Material Between III-V Channel Material and Insulator Layer - Improved semiconductor substrates are provided that employ a wide bandgap material between the channel and the insulator. A semiconductor substrate comprises a channel layer comprised of a III-V material; an insulator layer; and a wide bandgap material between the channel layer and the insulator layer, wherein a conduction band offset (ΔE) between the channel layer and the wide bandgap material is between 0.05 eV and 0.8 eV. The channel layer can be comprised of, for example, In | 08-01-2013 |
20130196488 | Fin Structures with Damage-Free Sidewalls for Multi-Gate Mosfets - Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (ΔE | 08-01-2013 |
20130200443 | Interface Engineering to Optimize Metal-III-V Contacts - Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact. | 08-08-2013 |
20130221373 | SOLAR CELL MADE USING A BARRIER LAYER BETWEEN P-TYPE AND INTRINSIC LAYERS - A method for forming a photovoltaic device includes depositing a p-type layer on a substrate. A barrier layer is formed on the p-type layer by exposing the p-type layer to an oxidizing agent. An intrinsic layer is formed on the barrier layer, and an n-type layer is formed on the intrinsic layer. | 08-29-2013 |
20130221464 | REDUCED LIGHT DEGRADATION DUE TO LOW POWER DEPOSITION OF BUFFER LAYER - Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a work function that falls substantially in a middle of a barrier formed between the transparent electrode and the p-type layer to provide a greater resistance to light induced degradation. An intrinsic layer and an n-type layer are formed over the p-type layer. | 08-29-2013 |
20130224899 | ENHANCING EFFICIENCY IN SOLAR CELLS BY ADJUSTING DEPOSITION POWER - Methods for forming a photovoltaic device include adjusting a deposition power for depositing a buffer layer including germanium on a transparent electrode. The deposition power is configured to improve device efficiency. A p-type layer is formed on the buffer layer. An intrinsic layer and an n-type layer are formed over the p-type layer. | 08-29-2013 |
20130224900 | SOLAR CELL MADE IN A SINGLE PROCESSING CHAMBER - Methods for forming a photovoltaic device include depositing a p-type layer on a substrate and cleaning the p-type layer by exposing a surface of the p-type layer to a plasma treatment to react with contaminants. An intrinsic layer is formed on the p-type layer, and an n-type layer is formed on the intrinsic layer. | 08-29-2013 |
20130240893 | BREAKDOWN VOLTAGE MULTIPLYING INTEGRATION SCHEME - A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both n-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions. | 09-19-2013 |
20130240951 | GALLIUM NITRIDE SUPERJUNCTION DEVICES - Gallium nitride high electron mobility transistor structures enable high breakdown voltages and are usable for high-power, and/or high-frequency switching. Schottky diodes facilitate high voltage applications and offer fast switching. A superjunction formed by p/n junctions in gallium nitride facilitates operation of the high electron mobility transistor structures and Schottky diodes as well as gated diodes formed by drain to gate connections of the transistor structures. Breakdown between the gate and drain of the high electron mobility transistor structures, through the substrate, or both is suppressed. | 09-19-2013 |
20130242627 | MONOLITHIC HIGH VOLTAGE MULTIPLIER - High voltage diode-connected gallium nitride high electron mobility transistor structures or Schottky diodes are employed in a network including high-k dielectric capacitors in a solid state, monolithic voltage multiplier. A superjunction formed by vertical p/n junctions in gallium nitride facilitates operation of the high electron mobility transistor structures and Schottky diodes. A design structure for designing, testing or manufacturing an integrated circuit is tangibly embodied in a machine-readable medium and includes elements of a solid state voltage multiplier. | 09-19-2013 |
20130244372 | SILICON PHOTOVOLTAIC ELEMENT AND FABRICATION METHOD - A method of forming a photovoltaic device that includes providing an absorption layer of a first crystalline semiconductor material having a first conductivity type, and epitaxially growing a second crystalline semiconductor layer of a second conductivity type that is opposite the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The temperature of the epitaxially growing the second crystalline semiconductor layer does not exceed 500° C. Contacts are formed in electrical communication with the absorption layer and the second crystalline semiconductor layer. | 09-19-2013 |
20130260505 | SOLAR-POWERED ENERGY-AUTONOMOUS SILICON-ON-INSULATOR DEVICE - A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures. | 10-03-2013 |
20130269860 | TEMPERATURE-CONTROLLED DEPTH OF RELEASE LAYER - A stressor layer is formed atop a base substrate at a first temperature which induces a first tensile stress in the base substrate that is below a fracture toughness of base substrate. The base substrate and the stressor layer are then brought to a second temperature which is less than the first temperature. The second temperature induces a second tensile stress in the stressor layer which is greater than the first tensile stress and which is sufficient to allow for spalling mode fracture to occur within the base substrate. The base substrate is spalled at the second temperature to form a spalled material layer. Spalling occurs at a fracture depth which is dependent upon the fracture toughness of the base substrate, stress level within the base substrate, and the second tensile stress of the stressor layer induced at the second temperature. | 10-17-2013 |
20130270608 | HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS - Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed. | 10-17-2013 |
20130280885 | LASER-INITIATED EXFOLIATION OF GROUP III-NITRIDE FILMS AND APPLICATIONS FOR LAYER TRANSFER AND PATTERNING - A pulsed laser-initiated exfoliation method for patterning a Group III-nitride film on a growth substrate is provided. This method includes providing a Group III-nitride film a growth substrate, wherein a growth substrate/Group III-nitride film interface is present between the Group III-nitride film and the growth substrate. Next, a laser is selected that provides radiation at a wavelength at which the Group III-nitride film is transparent and the growth substrate is absorbing. The interface is then irradiated with pulsed laser radiation from the Group III-nitride film side of the growth substrate/Group III-nitride film interface to exfoliate a region of the Group III-nitride from the growth substrate. A method for transfer a Group-III nitride film from a growth substrate to a handle substrate is also provided. | 10-24-2013 |
20130298971 | COST-EFFICENT HIGH POWER PECVD DEPOSITION FOR SOLAR CELLS - A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer. | 11-14-2013 |
20130298980 | CONE-SHAPED HOLES FOR HIGH EFFICIENCY THIN FILM SOLAR CELLS - A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided. | 11-14-2013 |
20130306971 | SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR - A high resolution active matrix backplane is fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed on a semiconductor-on-insulator substrate. The backplane layer is spalled from the substrate. A frontplane layer including passive devices such as LCDs, OLEDs, photosensitive materials, or piezo-electric materials is formed over the backplane layer to form an active matrix structure. The active matrix structure may be fabricated to allow bottom emission and provide mechanical flexibility. | 11-21-2013 |
20130307075 | CRYSTALLINE THIN-FILM TRANSISTORS AND METHODS OF FORMING SAME - Thin film transistors containing a gate structure on a crystalline semiconductor material including a crystalline active channel layer are provided. The gate structure of the present disclosure includes an insulator stack of, from bottom to top, a hydrogenated non-crystalline semiconductor material layer portion and a hydrogenated non-crystalline silicon nitride portion. Doped crystalline semiconductor source/drain regions are located on opposing sides of the gate structure and on surface portions of the crystalline semiconductor material. | 11-21-2013 |
20130309791 | SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR - A high resolution active matrix backplane is fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed on a semiconductor-on-insulator substrate. The backplane layer is spalled from the substrate. A frontplane layer including passive devices such as LCDs, OLEDs, photosensitive materials, or piezo-electric materials is formed over the backplane layer to form an active matrix structure. The active matrix structure may be fabricated to allow bottom emission and provide mechanical flexibility. | 11-21-2013 |
20130312819 | REMOVAL OF STRESSOR LAYER FROM A SPALLED LAYER AND METHOD OF MAKING A BIFACIAL SOLAR CELL USING THE SAME - A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell. | 11-28-2013 |
20130312828 | PHOTOVOLTAIC DEVICE WITH BAND-STOP FILTER - Photovoltaic device with band-stop filter. The photovoltaic device includes an amorphous photovoltaic material and a band-stop filter structure having a stopband extending from a lower limiting angular frequency ω | 11-28-2013 |
20130313551 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction. | 11-28-2013 |
20130313552 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH THIN EPITAXIAL CONTACTS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer. | 11-28-2013 |
20130316488 | REMOVAL OF STRESSOR LAYER FROM A SPALLED LAYER AND METHOD OF MAKING A BIFACIAL SOLAR CELL USING THE SAME - A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell. | 11-28-2013 |
20130316520 | METHODS OF FORMING CONTACT REGIONS USING SACRIFICIAL LAYERS - Methods of patterning semiconductor contact materials on a crystalline semiconductor material which allow high-quality interfaces between the crystalline semiconductor material and the patterned semiconductor contact material are provided. Blanket layers of passivation material and sacrificial material are formed on the crystalline semiconductor material. A first contact opening is formed into the blanker layer of sacrificial material. The first contact opening is extended into blanket layer of passivation material, stopping on a first surface portion of the crystalline semiconductor material, using remaining sacrificial material portions as an etch mask. A semiconductor contact material is formed on the exposed first surface portion of the crystalline semiconductor material. In some embodiments, an electrode material portion can be formed over the first contact opening, and then a second blanket layer of sacrificial material can be formed, followed by forming a next contact opening. | 11-28-2013 |
20130316538 | SURFACE MORPHOLOGY GENERATION AND TRANSFER BY SPALLING - The generation of surface patterns or the replication of surface patterns is achieved in the present disclosure without the need to employ an etching process. Instead, a unique fracture mode referred to as spalling is used in the present disclosure to generate or replicate surface patterns. In the case of surface pattern generation, a surface pattern is provided in a stressor layer and then spalling is performed. In the case of surface pattern replication, a surface pattern is formed within or on a surface of a base substrate, and then a stressor layer is applied. After applying the stressor layer, spalling is performed. Generation or replication of surface patterns utilizing spalling provides a low cost means for generation or replication of surface patterns. | 11-28-2013 |
20130316542 | SPALLING UTILIZING STRESSOR LAYER PORTIONS - A method for spalling local areas of a base substrate utilizing at least one stressor layer portion which is located on a portion, but not all, of an uppermost surface of a base substrate. The method includes providing a base substrate having a uniform thickness and a planar uppermost surface spanning across an entirety of the base substrate. At least one stressor layer portion having a shape is formed on at least a portion, but not all, of the uppermost surface of the base substrate. Spalling is performed which removes a material layer portion from the base substrate and provides a remaining base substrate portion. The material layer portion has the shape of the at least one stressor layer portion, while the remaining base substrate portion has at least one opening located therein which correlates to the shape of the at least one stressor layer. | 11-28-2013 |
20130320483 | SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES - Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å. | 12-05-2013 |
20130328110 | THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR - Junction field effect transistors are provided which include a gate junction located on a surface of a crystalline semiconductor material of a first conductivity type. The gate junction can be selected from one of a doped hydrogenated crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, a doped hydrogenated non-crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, and a Schottky contact. | 12-12-2013 |
20130334571 | EPITAXIAL GROWTH OF SMOOTH AND HIGHLY STRAINED GERMANIUM - A smooth germanium layer which can be grown directly on a silicon semiconductor substrate by exposing the substrate to germanium precursor in the presence of phosphine at temperature of about 350C. The germanium layer formation can be achieved with or without a SiGe seed layer. The process to form the germanium layer can be integrated into standard CMOS processing to efficiently form a structure embodying a thin, highly strained germanium layer. Such structure can enable processing flexibility. The germanium layer can also provide unique physical properties such as in an opto-electronic devices, or to enable formation of a layer of group III-V material on a silicon substrate. | 12-19-2013 |
20130341623 | PHOTORECEPTOR WITH IMPROVED BLOCKING LAYER - A photoreceptor includes a multilayer blocking structure to reduce dark discharge of the surface voltage of the photoreceptor resulting from electron injection from an electrically conductive substrate. The multilayer blocking structure includes wide band gap semiconductor layers in alternating sequence with one or more narrow band gap blocking layers. A fabrication method of the photoreceptor includes transfer-doping of the narrow band gap blocking layers, which are deposited in alternating sequence with wide band gap semiconductor layers to form a blocking structure. Suppression of hole or electron injection can be obtained using the method. | 12-26-2013 |
20130344644 | PHOTORECEPTOR WITH IMPROVED BLOCKING LAYER - A photoreceptor includes a multilayer blocking structure to reduce dark discharge of the surface voltage of the photoreceptor resulting from electron injection from an electrically conductive substrate. The multilayer blocking structure includes wide band gap semiconductor layers in alternating sequence with one or more narrow band gap blocking layers. A fabrication method of the photoreceptor includes transfer-doping of the narrow band gap blocking layers, which are deposited in alternating sequence with wide band gap semiconductor layers to form a blocking structure. Suppression of hole or electron injection can be obtained using the method. | 12-26-2013 |
20140000685 | HIGH EFFICIENCY SOLAR CELLS FABRICATED BY INEXPENSIVE PECVD | 01-02-2014 |
20140000692 | TRANSPARENT CONDUCTIVE ELECTRODE FOR THREE DIMENSIONAL PHOTOVOLTAIC DEVICE | 01-02-2014 |
20140004648 | TRANSPARENT CONDUCTIVE ELECTRODE FOR THREE DIMENSIONAL PHOTOVOLTAIC DEVICE | 01-02-2014 |
20140004651 | HIGH EFFICIENCY SOLAR CELLS FABRICATED BY INEXPENSIVE PECVD | 01-02-2014 |
20140007932 | FLEXIBLE III-V SOLAR CELL STRUCTURE - Solar cell structures include stacked layers in reverse order on a germanium substrate wherein a n++ (In)GaAs buffer layer plays dual roles as buffer and contact layers in the inverted structures. The absorbing layers employed in such exemplary structures are III-V layers such as (In)GaAs. Controlled spalling may be employed as part of the fabrication process for the solar cell structures, which may be single or multi-junction. The requirement for etching a buffer layer is eliminated, thereby facilitating the manufacturing process of devices using the disclosed structures. | 01-09-2014 |
20140008729 | STRAINED SILICON AND STRAINED SILICON GERMANIUM ON INSULATOR - A structure includes a tensilely strained nFET region including a strained silicon layer of a silicon on insulator wafer. A relaxed nFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer. A compressively strained pFET region includes a SiGe layer which was converted from a tensilely strained silicon layer of the silicon on insulator wafer. A relaxed pFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer. | 01-09-2014 |
20140014162 | EFFICIENCY RESTORATION IN A PHOTOVOLTAIC CELL - The electrical output efficiency of a photovoltaic thermal system can be restored from degradation due to light exposure by annealing a photovoltaic thermal cell at an elevated temperature. The elevated temperature at the photovoltaic thermal cell can be provided by redirecting the flow of a heat exchange fluid to bypass a heat exchanger unit. A boiler unit may be employed to provide additional heating of the heat exchange fluid during the anneal. Further, a variable configuration lid can be provided over a front surface of the photovoltaic thermal cell to control ventilation over the front surface. During the anneal, the position of the variable configuration lid can be set so as to trap heat above the front surface and to elevate the anneal temperature further. | 01-16-2014 |
20140034699 | METHOD FOR IMPROVING QUALITY OF SPALLED MATERIAL LAYERS - Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling. | 02-06-2014 |
20140045324 | LOW TEMPERATURE EPITAXY OF A SEMICONDUCTOR ALLOY INCLUDING SILICON AND GERMANIUM EMPLOYING A HIGH ORDER SILANE PRECURSOR - A high order silane having a formula of Si | 02-13-2014 |
20140048122 | HETEROSTRUCTURE GERMANIUM TANDEM JUNCTION SOLAR CELL - A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer. | 02-20-2014 |
20140048809 | SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR - A high resolution active matrix backplane is fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed on a semiconductor-on-insulator substrate. The backplane layer is spalled from the substrate. A frontplane layer including passive devices such as LCDs, OLEDs, photosensitive materials, or piezo-electric materials is formed over the backplane layer to form an active matrix structure. The active matrix structure may be fabricated to allow bottom emission and provide mechanical flexibility. | 02-20-2014 |
20140060627 | FIELD-EFFECT LOCALIZED EMITTER PHOTOVOLTAIC DEVICE - Photovoltaic structures are provided with field-effect inversion/accumulation layers as emitter layers induced by work-function differences between gate conductor layers and substrates thereof. Localized contact regions are in electrical communication with the gate conductors of such structures for repelling minority carriers. Such localized contact regions may include doped crystalline or polycrystalline silicon regions between the gate conductor and silicon absorption layers. Fabrication of the structures can be conducted without alignment between metal contacts and the localized contact regions or high temperature processing. | 03-06-2014 |
20140060628 | UNIFORMLY DISTRIBUTED SELF-ASSEMBLED SOLDER DOT FORMATION FOR HIGH EFFICIENCY SOLAR CELLS - A substrate for photovoltaic device includes a textured surface formed from silicon-based material. The textured surface includes a plurality of cones uniformly distributed across the textured surface. The uniformly distributed cones are configured by etching from a top surface of the substrate using a self-assembled solder dot mask evaporated on the substrate prior to etching. The cones are uniformly distributed as a result of gettering a process chamber prior to forming the solder dot mask. The cones have a height/width ratio between about 1 to about 4, and the cones have a density between 10 | 03-06-2014 |
20140065752 | UNIFORMLY DISTRIBUTED SELF-ASSEMBLED SOLDER DOT FORMATION FOR HIGH EFFICIENCY SOLAR CELLS - A method for fabricating a photovoltaic device includes performing a gettering process in a processing chamber which restricts formation of a layer of gettering materials on a substrate and forming a solder layer on the substrate. The solder layer is annealed to form uniformly distributed solder dots which grow on the substrate. The substrate is etched using the solder dots to protect portions of the substrate and form cones in the substrate such that the cones provide a three-dimensional radiation absorbing structure for the photovoltaic device. | 03-06-2014 |
20140070215 | DEFECT FREE STRAINED SILICON ON INSULATOR (SSOI) SUBSTRATES - A method of forming a strained semiconductor material that in one embodiment includes forming a cleave layer in a host semiconductor substrate, and contacting a strain inducing material layer on a surface of a transfer portion of the host semiconductor substrate. A handle substrate is then contacted to an exposed surface of the stress inducing material layer. The transfer portion of the host semiconductor substrate may then be separated from the host semiconductor substrate along the cleave layer. A dielectric layer is formed directly on the transfer portion of the host semiconductor substrate. The handle substrate and the stress inducing material are then removed, wherein the transferred portion of the host semiconductor substrate provides a strained semiconductor layer that is in direct contact with a dielectric layer. | 03-13-2014 |
20140073119 | DEFECT FREE STRAINED SILICON ON INSULATOR (SSOI) SUBSTRATES - A method of forming a strained semiconductor material that in one embodiment includes forming a cleave layer in a host semiconductor substrate, and contacting a strain inducing material layer on a surface of a transfer portion of the host semiconductor substrate. A handle substrate is then contacted to an exposed surface of the stress inducing material layer. The transfer portion of the host semiconductor substrate may then be separated from the host semiconductor substrate along the cleave layer. A dielectric layer is formed directly on the transfer portion of the host semiconductor substrate. The handle substrate and the stress inducing material are then removed, wherein the transferred portion of the host semiconductor substrate provides a strained semiconductor layer that is in direct contact with a dielectric layer. | 03-13-2014 |
20140077210 | AMORPHOUS SILICON PHOTODETECTOR WITH LOW DARK CURRENT - A p-i-n photodetector includes at least one multilayer contact structure including wide gap and narrow gap layers to reduce dark current. The multilayer contact structure includes one or more wide band gap semiconductor layers in alternating sequence with one or more narrow band gap contact layers. A fabrication method of the photodetector includes transfer-doping of the narrow band gap contact layers, which are deposited in alternating sequence with wide band gap semiconductor layers. | 03-20-2014 |
20140083506 | EMBEDDED JUNCTION IN HETERO-STRUCTURED BACK-SURFACE FIELD FOR PHOTOVOLTAIC DEVICES - A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate. | 03-27-2014 |
20140084251 | ZINC OXIDE-CONTAINING TRANSPARENT CONDUCTIVE ELECTRODE - A transparent conductive electrode stack containing a work function adjusted zinc oxide is provided. Specifically, the transparent conductive electrode stack includes a layer of zinc oxide and a layer of a work function modifying material. The presence of the work function modifying material in the transparent conductive electrode stack shifts the work function of the layer of zinc oxide to a higher value for better hole injection into the OLED device as compared to a transparent conductive electrode that includes only a layer of zinc oxide and no work function modifying material. | 03-27-2014 |
20140084252 | DOPED GRAPHENE TRANSPARENT CONDUCTIVE ELECTRODE - Graphene is used as a replacement for indium tin oxide as a transparent conductive electrode which can be used in an organic light emitting diode (OLED) device. Using graphene reduces the cost of manufacturing OLED devices and also makes the OLED device extremely flexible. The graphene is chemically doped so that the work function of the graphene is shifted to a higher value for better hole injection into the OLED device as compared to an OLED device containing an undoped layer of graphene. An interfacial layer comprising a conductive polymer and/or metal oxide can also be used to further reduce the remaining injection barrier. | 03-27-2014 |
20140084253 | TRANSPARENT CONDUCTIVE ELECTRODE STACK CONTAINING CARBON-CONTAINING MATERIAL - A transparent conductive electrode stack containing a work function adjusted carbon-containing material is provided. Specifically, the transparent conductive electrode stack includes a layer of a carbon-containing material and a layer of a work function modifying material. The presence of the work function modifying material in the transparent conductive electrode stack shifts the work function of the layer of carbon-containing material to a higher value for better hole injection into the OLED device as compared to a transparent conductive electrode that includes only a layer of carbon-containing material and no work function modifying material. | 03-27-2014 |
20140084254 | OLED DISPLAY WITH SPALLED SEMICONDUCTOR DRIVING CIRCUITRY AND OTHER INTEGRATED FUNCTIONS - Spalling is employed to generate a single crystalline semiconductor layer. Complementary metal oxide semiconductor (CMOS) logic and memory devices are formed on a single crystalline semiconductor substrate prior to spalling. Organic light emitting diode (OLED) driving circuitry, solar cells, sensors, batteries and the like can be formed prior to, or after, spalling. The spalled single crystalline semiconductor layer can be transferred to a substrate. OLED displays can be formed into the spalled single crystalline semiconductor layer to achieve a structure including an OLED display with semiconductor driving circuitry and other functions integrated on the single crystalline semiconductor layer. | 03-27-2014 |
20140087500 | TRANSPARENT CONDUCTIVE ELECTRODE STACK CONTAINING CARBON-CONTAINING MATERIAL - A transparent conductive electrode stack containing a work function adjusted carbon-containing material is provided. Specifically, the transparent conductive electrode stack includes a layer of a carbon-containing material and a layer of a work function modifying material. The presence of the work function modifying material in the transparent conductive electrode stack shifts the work function of the layer of carbon-containing material to a higher value for better hole injection into the OLED device as compared to a transparent conductive electrode that includes only a layer of carbon-containing material and no work function modifying material. | 03-27-2014 |
20140087501 | DOPED GRAPHENE TRANSPARENT CONDUCTIVE ELECTRODE - Graphene is used as a replacement for indium tin oxide as a transparent conductive electrode which can be used in an organic light emitting diode (OLED) device. Using graphene reduces the cost of manufacturing OLED devices and also makes the OLED device extremely flexible. The graphene is chemically doped so that the work function of the graphene is shifted to a higher value for better hole injection into the OLED device as compared to an OLED device containing an undoped layer of graphene. An interfacial layer comprising a conductive polymer and/or metal oxide can also be used to further reduce the remaining injection barrier. | 03-27-2014 |
20140087504 | OLED DISPLAY WITH SPALLED SEMICONDUCTOR DRIVING CIRCUITRY AND OTHER INTEGRATED FUNCTIONS - Spalling is employed to generate a single crystalline semiconductor layer. Complementary metal oxide semiconductor (CMOS) logic and memory devices are formed on a single crystalline semiconductor substrate prior to spalling. Organic light emitting diode (OLED) driving circuitry, solar cells, sensors, batteries and the like can be formed prior to, or after, spalling. The spalled single crystalline semiconductor layer can be transferred to a substrate. OLED displays can be formed into the spalled single crystalline semiconductor layer to achieve a structure including an OLED display with semiconductor driving circuitry and other functions integrated on the single crystalline semiconductor layer. | 03-27-2014 |
20140087506 | ZINC OXIDE-CONTAINING TRANSPARENT CONDUCTIVE ELECTRODE - A transparent conductive electrode stack containing a work function adjusted zinc oxide is provided. Specifically, the transparent conductive electrode stack includes a layer of zinc oxide and a layer of a work function modifying material. The presence of the work function modifying material in the transparent conductive electrode stack shifts the work function of the layer of zinc oxide to a higher value for better hole injection into the OLED device as compared to a transparent conductive electrode that includes only a layer of zinc oxide and no work function modifying material. | 03-27-2014 |
20140087513 | EMBEDDED JUNCTION IN HETERO-STRUCTURED BACK-SURFACE FIELD FOR PHOTOVOLTAIC DEVICES - A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate. | 03-27-2014 |
20140091370 | TRANSISTOR FORMATION USING COLD WELDING - A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device. | 04-03-2014 |
20140094006 | TRANSISTOR FORMATION USING COLD WELDING - A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device. | 04-03-2014 |
20140109961 | COMPOSITIONALLY-GRADED BAND GAP HETEROJUNCTION SOLAR CELL - A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device. | 04-24-2014 |
20140120655 | ENHANCING EFFICIENCY IN SOLAR CELLS BY ADJUSTING DEPOSITION POWER - Methods for forming a photovoltaic device include adjusting a deposition power for depositing a buffer layer including germanium on a transparent electrode. The deposition power is configured to improve device efficiency. A p-type layer is formed on the buffer layer. An intrinsic layer and an n-type layer are formed over the p-type layer. | 05-01-2014 |
20140124019 | LOW VACUUM FABRICATION OF MICROCRYSTALLINE SOLAR CELLS - A device and method for forming a photovoltaic device include forming a photovoltaic stack of layers on a transparent substrate wherein at least one layer of the photovoltaic stack of layers includes a microcrystalline layer. The microcrystalline layer is formed by purging a vacuum chamber with a gettering gas to remove contaminant species from the chamber prior to forming the microcrystalline layer. The microcrystalline layer is deposited at a vacuum base pressure of greater than about 10 | 05-08-2014 |
20140124033 | UNIFORMLY DISTRIBUTED SELF-ASSEMBLED CONE-SHAPED PILLARS FOR HIGH EFFICIENCY SOLAR CELLS - A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device. | 05-08-2014 |
20140124795 | DOUBLE LAYERED TRANSPARENT CONDUCTIVE OXIDE FOR REDUCED SCHOTTKY BARRIER IN PHOTOVOLTAIC DEVICES - A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer. | 05-08-2014 |
20140127852 | LOW VACUUM FABRICATION OF MICROCRYSTALLINE SOLAR CELLS - A device and method for forming a photovoltaic device include forming a photovoltaic stack of layers on a transparent substrate wherein at least one layer of the photovoltaic stack of layers includes a microcrystalline layer. The microcrystalline layer is formed by purging a vacuum chamber with a gettering gas to remove contaminant species from the chamber prior to forming the microcrystalline layer. The microcrystalline layer is deposited at a vacuum base pressure of greater than about 10 | 05-08-2014 |
20140127853 | DOUBLE LAYERED TRANSPARENT CONDUCTIVE OXIDE FOR REDUCED SCHOTTKY BARRIER IN PHOTOVOLTAIC DEVICES - A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer. | 05-08-2014 |
20140131287 | ELECTRICITY-LESS WATER DISINFECTION - Disinfecting a sample of water includes generating a current using an array of photovoltaic cells, using the current to power an array of light emitting diodes, wherein the array of light emitting diodes emits a germicidal wavelength of radiation, and exposing the sample of water to the radiation. Another method for disinfecting a sample of water includes placing the sample of water within a container, wherein the container includes an array of photovoltaic cells encircling an exterior wall of the container and an array of light emitting diodes encircling an interior wall of the container, placing the container in a location exposed to solar radiation, converting the solar radiation to a current using the array of photovoltaic cells, and powering the array of light emitting diodes using the current, wherein the array of light emitting diodes emits a germicidal wavelength of radiation sufficient to disinfect the sample of water. | 05-15-2014 |
20140131591 | ELECTRICITY-LESS WATER DISINFECTION - A system for disinfecting a sample of water includes a container for holding the sample of water, an array of photovoltaic cells coupled to the container for converting solar radiation into a current, and an array of light emitting diodes coupled to the container and powered by the current, wherein the array of light emitting diodes emits a germicidal wavelength of radiation. Another system for disinfecting a sample of water includes a container for holding the sample of water, an array of photovoltaic cells encircling an exterior wall of the container, for converting solar radiation into a current, and an array of light emitting diodes encircling an interior wall of the container and powered by the current, wherein the array of light emitting diodes emits a germicidal wavelength of radiation. | 05-15-2014 |
20140131722 | DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON - A method for selective formation of a dual phase gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patterned dielectric material structures on silicon substrate. An etch is employed that selectively removes exposed portions of the silicon substrate. The etch forms openings within the silicon substrate that expose a surface of the silicon substrate having a (111) crystal plane. A contiguous AlN buffer layer is then formed on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate. A dual phase gallium nitride material is then formed on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure. | 05-15-2014 |
20140131724 | SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON - A method for selective formation of a gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patterned dielectric material structures on silicon substrate. An etch is employed that selectively removes exposed portions of the silicon substrate. The etch forms openings within the silicon substrate that expose a surface of the silicon substrate having a (111) crystal plane. A contiguous AlN buffer layer is then formed on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate. A gallium nitride material is then formed on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure. | 05-15-2014 |
20140131770 | CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES - First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate. | 05-15-2014 |
20140134811 | CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES - First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate. | 05-15-2014 |
20140134830 | SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON - A method for selective formation of a gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patterned dielectric material structures on silicon substrate. An etch is employed that selectively removes exposed portions of the silicon substrate. The etch forms openings within the silicon substrate that expose a surface of the silicon substrate having a (111) crystal plane. A contiguous AlN buffer layer is then formed on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate. A gallium nitride material is then formed on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure. | 05-15-2014 |
20140138781 | DIELECTRIC EQUIVALENT THICKNESS AND CAPACITANCE SCALING FOR SEMICONDUCTOR DEVICES - A device and method for fabricating a capacitive component includes forming a high dielectric constant material over a semiconductor substrate and forming a scavenging layer on the high dielectric constant material. An anneal process forms oxide layer between the high dielectric constant layer and the scavenging layer such that oxygen in the high dielectric constant material is drawn out to reduce oxygen content. | 05-22-2014 |
20140147988 | FIXED CURVATURE FORCE LOADING OF MECHANICALLY SPALLED FILMS - A spalling method is provided that includes depositing a stressor layer on surface of a base substrate, and contacting the stressor layer with a planar transfer. The planar transfer surface is then traversed along a plane that is parallel to and having a vertical offset from the upper surface of the base substrate. The planar transfer surface is traversed in a direction from a first edge of the base substrate to an opposing second edge of the base substrate to cleave the base substrate and transfer a spalled portion of the base substrate to the planar transfer surface. The vertical offset between the plane along which the planar transfer surface is traversed and the upper surface of the base substrate is a fixed distance. The fixed distance of the vertical offset provides a uniform spalling force. A spalling method is also provided that includes a transfer roller. | 05-29-2014 |
20140158187 | SELECTIVE EMITTER PHOTOVOLTAIC DEVICE - A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device. | 06-12-2014 |
20140162396 | SELECTIVE EMITTER PHOTOVOLTAIC DEVICE - A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device. | 06-12-2014 |
20140166079 | MONOLITHIC INTEGRATION OF HETEROJUNCTION SOLAR CELLS - A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure. | 06-19-2014 |
20140166096 | FIELD-EFFECT INTER-DIGITATED BACK CONTACT PHOTOVOLTAIC DEVICE - A method for forming a photovoltaic device includes patterning a dielectric layer on a substrate to form a patterned dielectric having local spacings between shapes and remote spacings between groups of shapes, and depositing a doped epitaxial layer over the patterned dielectric such that selective crystalline growth occurs in portions of the epitaxial layer in contact with the substrate and noncrystalline growth occurs in portions of the epitaxial layer in contact with the patterned dielectric. First metal contacts are formed over the local spacings of the patterned dielectric, and second metal contacts are formed over the remote spacings. Exposed portions of the noncrystalline growth are etched using the first and second metal contacts as an etch mask to form alternating interdigitated emitter and back contact stacks. | 06-19-2014 |
20140170807 | MONOLITHIC INTEGRATION OF HETEROJUNCTION SOLAR CELLS - A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure. | 06-19-2014 |
20140179045 | TRANSPARENT CONDUCTIVE ELECTRODE STACK CONTAINING CARBON-CONTAINING MATERIAL - A transparent conductive electrode stack containing a work function adjusted carbon-containing material is provided. Specifically, the transparent conductive electrode stack includes a layer of a carbon-containing material and a layer of a work function modifying material. The presence of the work function modifying material in the transparent conductive electrode stack shifts the work function of the layer of carbon-containing material to a higher value for better hole injection into the OLED device as compared to a transparent conductive electrode that includes only a layer of carbon-containing material and no work function modifying material. | 06-26-2014 |
20140183686 | AUTONOMOUS INTEGRATED CIRCUITS - An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer. | 07-03-2014 |
20140190564 | HETEROJUNCTION III-V SOLAR CELL PERFORMANCE | 07-10-2014 |
20140191237 | CRYSTALLINE THIN-FILM TRANSISTOR - A method for forming a thin film transistor includes joining a crystalline substrate to an insulating substrate. A doped layer is deposited on the crystalline substrate, and the doped layer is patterned to form source and drain regions. The crystalline substrate is patterned to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions. A gate stack is formed between the source and drain regions, and contacts are formed to the source and drain regions and the gate stack through a passivation layer. | 07-10-2014 |
20140191283 | GROUP III NITRIDES ON NANOPATTERNED SUBSTRATES - A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III nitride material is grown atop the mesa surface portions of the patterned substrate and atop the recessed surface. Growth of the Group III nitride material is continued merging the Group III nitride material that is grown atop the mesa surface portions. When the Group III nitride material located atop the mesa surface portions merge, the Group III nitride material growth on the recessed surface ceases. The merged Group III nitride material forms a first Group III nitride material structure, and the Group III nitride material formed in the recessed surface forms a second material structure. The first and second material structures are disjoined from each other and are separated by an air gap. | 07-10-2014 |
20140191284 | GROUP III NITRIDES ON NANOPATTERNED SUBSTRATES - A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III nitride material is grown atop the mesa surface portions of the patterned substrate and atop the recessed surface. Growth of the Group III nitride material is continued merging the Group III nitride material that is grown atop the mesa surface portions. When the Group III nitride material located atop the mesa surface portions merge, the Group III nitride material growth on the recessed surface ceases. The merged Group III nitride material forms a first Group III nitride material structure, and the Group III nitride material formed in the recessed surface forms a second material structure. The first and second material structures are disjoined from each other and are separated by an air gap. | 07-10-2014 |
20140191320 | CRYSTALLINE THIN-FILM TRANSISTOR - A method for forming a thin film transistor includes joining a crystalline substrate to an insulating substrate. A doped layer is deposited on the crystalline substrate, and the doped layer is patterned to form source and drain regions. The crystalline substrate is patterned to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions. A gate stack is formed between the source and drain regions, and contacts are formed to the source and drain regions and the gate stack through a passivation layer. | 07-10-2014 |
20140196773 | MULTI-JUNCTION III-V SOLAR CELL - A multi junction solar cell structure includes a top photovoltaic cell including III-V semiconductor materials and a silicon-based bottom photovoltaic cell. A thin, germanium-rich silicon germanium buffer layer is provided between the top and bottom cells. Fabrication techniques for producing multi junction III-V solar cell structures, lattice-matched or pseudomorphic to germanium, on silicon substrates is further provided wherein silicon serves as the bottom cell. The open circuit voltage of the silicon cell may be enhanced by localized back surface field structures, localized back contacts, or amorphous silicon-based heterojunction back contacts. | 07-17-2014 |
20140196774 | MULTI-JUNCTION III-V SOLAR CELL - A multi junction solar cell structure includes a top photovoltaic cell including III-V semiconductor materials and a silicon-based bottom photovoltaic cell. A thin, germanium-rich silicon germanium buffer layer is provided between the top and bottom cells. Fabrication techniques for producing multi junction III-V solar cell structures, lattice-matched or pseudomorphic to germanium, on silicon substrates is further provided wherein silicon serves as the bottom cell. The open circuit voltage of the silicon cell may be enhanced by localized back surface field structures, localized back contacts, or amorphous silicon-based heterojunction back contacts. | 07-17-2014 |
20140196780 | PHOTOVOLTAIC DEVICES WITH AN INTERFACIAL BAND-GAP MODIFYING STRUCTURE AND METHODS FOR FORMING THE SAME - A Schottky-barrier-reducing layer is provided between a p-doped semiconductor layer and a transparent conductive material layer of a photovoltaic device. The Schottky-barrier-reducing layer can be a conductive material layer having a work function that is greater than the work function of the transparent conductive material layer. The conductive material layer can be a carbon-material layer such as a carbon nanotube layer or a graphene layer. Alternately, the conductive material layer can be another transparent conductive material layer having a greater work function than the transparent conductive material layer. The reduction of the Schottky barrier reduces the contact resistance across the transparent material layer and the p-doped semiconductor layer, thereby reducing the series resistance and increasing the efficiency of the photovoltaic device. | 07-17-2014 |
20140216534 | BUFFER LAYER FOR HIGH PERFORMING AND LOW LIGHT DEGRADED SOLAR CELLS - Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a doped germanium-free silicon base material. The buffer layer has a work function that falls within barrier energies of the transparent electrode and the p-type layer. An intrinsic layer and an n-type layer are formed on the p-type layer. Devices are also provided. | 08-07-2014 |
20140217356 | THIN FILM WAFER TRANSFER AND STRUCTURE FOR ELECTRONIC DEVICES - An electronic device includes a spreading layer and a first contact layer formed over and contacting the spreading layer. The first contact layer is formed from a thermally conductive crystalline material having a thermal conductivity greater than or equal to that of an active layer material. An active layer includes one or more III-nitride layers. A second contact layer is formed over the active layer, wherein the active layer is disposed vertically between the first and second contact layers to form a vertical thin film stack. | 08-07-2014 |
20140217408 | BUFFER LAYER FOR HIGH PERFORMING AND LOW LIGHT DEGRADED SOLAR CELLS - Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a doped germanium-free silicon base material. The buffer layer has a work function that falls within barrier energies of the transparent electrode and the p-type layer. An intrinsic layer and an n-type layer are formed on the p-type layer. Devices are also provided. | 08-07-2014 |
20140217468 | PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL - A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided. | 08-07-2014 |
20140220764 | THIN FILM WAFER TRANSFER AND STRUCTURE FOR ELECTRONIC DEVICES - A method for wafer transfer includes forming a spreading layer, including graphene, on a single crystalline SiC substrate. A semiconductor layer including one or more layers is formed on and is lattice matched to the crystalline SiC layer. The semiconductor layer is transferred to a handle substrate, and the spreading layer is split to remove the single crystalline SiC substrate. | 08-07-2014 |
20140220766 | PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL - A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided. | 08-07-2014 |
20140242746 | ELECTRODE FORMATION FOR HETEROJUNCTION SOLAR CELLS - A method for forming a photovoltaic device includes forming a doped layer on a crystalline substrate, the doped layer having an opposite dopant conductivity as the substrate. A non-crystalline transparent conductive electrode (TCE) layer is formed on the doped layer at a temperature less than 150 degrees Celsius. The TCE layer is flash annealed to crystallize material of the TCE layer at a temperature above about 150 degrees Celsius for less than 10 seconds. | 08-28-2014 |
20140242807 | METHOD FOR FACILITATING CRACK INITIATION DURING CONTROLLED SUBSTRATE SPALLING - A method is provided in which a substrate including various materials of different fracture toughness (K | 08-28-2014 |
20140251548 | METHOD FOR IMPROVING SURFACE QUALITY OF SPALLED SUBSTRATES - A compliant material is formed between a base substrate and a support structure prior to performing a controlled spalling process. By positioning the compliant material between the base substrate and the support structure, the localized effects of surface perturbations (particles, wafer artifacts, etc.) on spalling mode fracture can be reduced. The method of the present disclosure thus leads to improved surface quality of the spalled material layer and the remaining base substrate. Moreover, the method of the present disclosure can reduce the density of cleaving artifacts. | 09-11-2014 |
20140264446 | III-V FINFETS ON SILICON SUBSTRATE - A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material. | 09-18-2014 |
20140264607 | III-V FINFETS ON SILICON SUBSTRATE - A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material. | 09-18-2014 |
20140291282 | WAFER SCALE EPITAXIAL GRAPHENE TRANSFER - A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a substrate, the spreading layer having a monolayer. A stressor layer is formed on the spreading layer, and the stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein the closest monolayer remains on the stressor layer. | 10-02-2014 |
20140312094 | SUBSTRATE HOLDER ASSEMBLY FOR CONTROLLED LAYER TRANSFER - A substrate holder assembly for use in a controlled spalling process is provided. The substrate holder assembly includes a base structure having a surface in which a base substrate or other work piece can be placed thereupon. A framing element is located above and spaced apart from the surface of the base structure. The framing element has a window which exposes an upper surface of the base substrate and defines an area of the upper surface of the base substrate in which another material can be applied thereto. A support structure containing at least one mechanical securing element is located on the framing element. The support structure mechanically constrains the base substrate within the substrate holder assembly. Each mechanical securing element contacts at least one surface of the support structure and, optionally, one surface of the base substrate. | 10-23-2014 |
20140312576 | SUBSTRATE HOLDER ASSEMBLY FOR CONTROLLED LAYER TRANSFER - A substrate holder assembly for use in a controlled spalling process is provided. The substrate holder assembly includes a base structure having a surface in which a base substrate or other work piece can be placed thereupon. A framing element is located above and spaced apart from the surface of the base structure. The framing element has a window which exposes an upper surface of the base substrate and defines an area of the upper surface of the base substrate in which another material can be applied thereto. A support structure containing at least one mechanical securing element is located on the framing element. The support structure mechanically constrains the base substrate within the substrate holder assembly. Each mechanical securing element contacts at least one surface of the support structure and, optionally, one surface of the base substrate. | 10-23-2014 |
20140315389 | CRACK CONTROL FOR SUBSTRATE SEPARATION - A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack. | 10-23-2014 |
20140332851 | REDUCED SHORT CHANNEL EFFECT OF III-V FIELD EFFECT TRANSISTOR VIA OXIDIZING ALUMINUM-RICH UNDERLAYER - In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region. | 11-13-2014 |
20140332855 | REDUCED SHORT CHANNEL EFFECT OF III-V FIELD EFFECT TRANSISTOR VIA OXIDIZING ALUMINUM-RICH UNDERLAYER - In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region. | 11-13-2014 |
20140353698 | HETEROJUNCTION LIGHT EMITTING DIODE - A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer. | 12-04-2014 |
20140353700 | HETEROJUNCTION LIGHT EMITTING DIODE - A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer. | 12-04-2014 |
20150014778 | MULTIPLE VIA STRUCTURE AND METHOD - A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts. | 01-15-2015 |
20150035123 | CURVATURE COMPENSATED SUBSTRATE AND METHOD OF FORMING SAME - A curvature-control-material (CCM) is formed on one side of a substrate prior to forming a Group III nitride material on the other side of the substrate. The CCM possess a thermal expansion coefficient (TEC) that is lower than the TEC of the substrate and is stable at elevated growth temperatures required for formation of a Group III nitride material. In some embodiments, the deposition conditions of the CCM enable a flat-wafer condition for the Group III nitride material maximizing the emission wavelength uniformity of the Group III nitride material. Employment of the CCM also reduces the final structure bowing during cool down leading to reduced convex substrate curvatures. In some embodiments, the final structure curvature can further be engineered to be concave by proper selection of CCM properties, and via controlled selective etching of the CCM, this method enables the final structure to be flat. | 02-05-2015 |
20150041756 | THIN LIGHT EMITTING DIODE AND FABRICATION METHOD - A method for fabrication a light emitting diode (LED) includes growing a crystalline LED structure on a growth substrate, forming alternating material layers on the LED structure to form a reflector on a back side opposite the growth substrate and depositing a stressor layer on the reflector. A handle substrate is adhered to the stressor layer. The LED structure is separated from the growth substrate using a spalling process to expose a front side of the LED structure. | 02-12-2015 |
20150044796 | THIN LIGHT EMITTING DIODE AND FABRICATION METHOD - A method for fabrication a light emitting diode (LED) includes forming alternating material layers on an LED structure, formed on a substrate, to form a reflector on a back side opposite the substrate. A handle substrate is adhered to a stressor layer deposited on the reflector. The LED structure is separated from the substrate using a spalling process to expose a front side of the LED structure. | 02-12-2015 |
20150047704 | III-V PHOTOVOLTAIC ELEMENTS - Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of Si | 02-19-2015 |
20150048422 | A METHOD FOR FORMING A CRYSTALLINE COMPOUND III-V MATERIAL ON A SINGLE ELEMENT SUBSTRATE - A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench. | 02-19-2015 |
20150048423 | SEMICONDUCTOR DEVICE HAVING A III-V CRYSTALLINE COMPOUND MATERIAL SELECTIVELY GROWN ON THE BOTTOM OF A SPACE FORMED IN A SINGLE ELEMENT SUBSTRATE. - A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench. | 02-19-2015 |
20150050769 | SOLAR-POWERED ENERGY-AUTONOMOUS SILICON-ON-INSULATOR DEVICE - A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures. | 02-19-2015 |
20150059841 | SELECTIVE EMITTER PHOTOVOLTAIC DEVICE - A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device. | 03-05-2015 |
20150060759 | TUNABLE LIGHT-EMITTING DIODE - A method of forming a light-emitting diode including determining a first level of tensile stress to be applied to a base substrate including a plurality of quantum well layers to adjust a band-gap of the base substrate to a predetermined band-gap. The first level of tensile stress is generated in the base substrate by forming a tensile-stressing layer on the base substrate. | 03-05-2015 |
20150060760 | TUNABLE LIGHT-EMITTING DIODE - A light-emitting diode device includes a base substrate including a plurality of quantum well layers, a first electrode on one side of the plurality of quantum well layers, and a second electrode on an opposite side of the plurality of quantum well layers. The device includes a tensile-stressing layer formed on the base substrate and having a thickness and chemical composition configured to generate a first tensile stress in the base substrate, the first compressive stress selected to cause the base substrate to have a predetermined band-gap. | 03-05-2015 |
20150068604 | SPALLING METHODS TO FORM MULTI-JUNCTION PHOTOVOLTAIC STRUCTURE - A method cleaving a semiconductor material that includes providing a germanium substrate having a germanium and tin alloy layer is present therein. A stressor layer is deposited on a surface of the germanium substrate. A stress from the stressor layer is applied to the germanium substrate, in which the stress cleaves the germanium substrate to provide a cleaved surface. The cleaved surface of the germanium substrate is then selective to the germanium and tin alloy layer of the germanium substrate. In another embodiment, the germanium and tin alloy layer may function as a fracture plane during a spalling method. | 03-12-2015 |
20150075608 | PHOTOVOLTAIC DEVICE USING NANO-SPHERES FOR TEXTURED ELECTRODES - An electronic device includes a substrate and a plurality of particles anchored to the substrate. An electrode material is formed over the particles and configured to form peaks over the particles. One or more operational layers are formed over the electrode material for performing a device function. | 03-19-2015 |
20150083036 | GALLIUM NITRIDE MATERIAL AND DEVICE DEPOSITION ON GRAPHENE TERMINATED WAFER AND METHOD OF FORMING THE SAME - A method of forming an epitaxial semiconductor material that includes forming a graphene layer on a semiconductor and carbon containing substrate and depositing a metal containing monolayer on the graphene layer. An epitaxial layer of a gallium containing material is formed on the metal containing monolayer. A layered stack of the metal containing monolayer and the epitaxial layer of gallium containing material is cleaved from the graphene layer that is present on the semiconductor and carbon containing substrate. | 03-26-2015 |
20150083224 | TRANSFERABLE TRANSPARENT CONDUCTIVE OXIDE - A method for fabricating a photovoltaic device includes forming an adhesion layer on a substrate, forming a material layer on the adhesion layer and applying release tape to the material layer. The substrate is removed at a weakest interface between the adhesion layer and the substrate by mechanically pulling the release tape to form a transfer substrate including the adhesion layer, the material layer and the release tape. The transfer substrate is transferred to a target substrate to contact the adhesion layer to the target substrate. The transfer substrate includes a material sensitive to formation processes of the transfer substrate such that exposure to the formation processes of the transfer substrate is avoided by the target substrate. | 03-26-2015 |
20150084004 | TRANSFERABLE TRANSPARENT CONDUCTIVE OXIDE - A method for fabricating a photovoltaic device includes forming an adhesion layer on a substrate, forming a material layer on the adhesion layer and applying release tape to the material layer. The substrate is removed at a weakest interface between the adhesion layer and the substrate by mechanically pulling the release tape to form a transfer substrate including the adhesion layer, the material layer and the release tape. The transfer substrate is transferred to a target substrate to contact the adhesion layer to the target substrate. The transfer substrate includes a material sensitive to formation processes of the transfer substrate such that exposure to the formation processes of the transfer substrate is avoided by the target substrate. | 03-26-2015 |
20150084074 | GALLIUM NITRIDE MATERIAL AND DEVICE DEPOSITION ON GRAPHENE TERMINATED WAFER AND METHOD OF FORMING THE SAME - A method of forming an epitaxial semiconductor material that includes forming a graphene layer on a semiconductor and carbon containing substrate and depositing a metal containing monolayer on the graphene layer. An epitaxial layer of a gallium containing material is formed on the metal containing monolayer. A layered stack of the metal containing monolayer and the epitaxial layer of gallium containing material is cleaved from the graphene layer that is present on the semiconductor and carbon containing substrate. | 03-26-2015 |