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Devarapalli, US
Malla Reddy Devarapalli, North Andover, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20100039237 | FRAMEWORK FOR FAST RFID TAG READING IN STATIC AND MOBILE ENVIRONMENTS - An RFID reader for reading RFID tags is disclosed. The RFID reader is provided with a clock generating clock signals; a transceiver; a control unit receiving the clock signals; and a memory accessible by the control unit and storing computer executable instructions to cause the control unit to generate a communication schedule based upon confirmed reservation requests, and to read RFID tags employing the communication schedule. A RFID tag is also disclosed. The tag is provided with transmit/receive circuitry; a clock; a control unit; powering up circuitry including a power source; and memory storing an electronic product code (EPC). The memory also stores computer executable instructions that cause the control unit to receive a broadcast from a reader; synchronize the clock of the tag with the reader; generate and transmit a reservation request; receive a reservation summary including a reserved time to transmit; transmit the EPC; and receive an acknowledgement. | 02-18-2010 |
Sreenivasulu Devarapalli, Louisville, KY US
| Patent application number | Description | Published |
|---|---|---|
| 20090243590 | SYSTEM AND METHOD FOR MONITORING CURRENT IN A CONDUCTOR - The present disclosure describes a system for measuring current amplitude in a conductor, comprising at least one Rogowski coil, an integration circuit directly connected to the at least one Rogowski coil, a microprocessor circuit in communication with the integration circuit and configured to receive output from the integration circuit and to calculate energy data comprising current amplitude in the conductor. A method for measuring current in a conductor is also presented. | 10-01-2009 |
Sreenivasulu R. Devarapalli, Louisville, KY US
| Patent application number | Description | Published |
|---|---|---|
| 20090256426 | SYSTEM AND METHOD FOR MANAGING POWER SUPPLY TO A CIRCUIT BREAKER CONTROL UNIT - A system for controlling power in a circuit breaker trip unit is disclosed. The system includes: a user interface operably coupled to the trip unit and having a plurality of input keys; a power conditioner operably coupled to the user interface and operably coupled to a battery power source and an external power source; and a power control circuit. The power control circuit is configured to automatically electrically connect the battery power source to the power conditioner in response to activation of any of the plurality of input keys, and in the absence of an electrical connection between the external power source and the power conditioner. | 10-15-2009 |
| 20090257163 | CURRENT GAIN CONTROL OF CIRCUIT BREAKER TRIP UNIT - An electronic trip unit for a circuit breaker, the electronic trip unit includes a rating plug having a plurality of switches each configured to indicate a specified current rating for the rating plug and for selectively supplying a current rating for the electronic trip unit, a processing unit which receives and reads a value of the selected current rating from the rating plug upon power-up, and a gain control unit including a plurality of gain circuits. Each of the gain circuits including a plurality of gain switches set by the processing unit based upon the selected current rating, to control a gain of input current of the electronic trip unit. | 10-15-2009 |
Sreenivasulu Reddy Devarapalli, Louisville, KY US
| Patent application number | Description | Published |
|---|---|---|
| 20090147424 | CIRCUIT BREAKERS WITH AUTOMATIC BREAKER RATING - An electronic control for a circuit breaker with automatic breaker rating is disclosed. The electronic control includes a memory to store circuit breaker ratings, a breaker rating switch to select circuit breaker ratings, and a microprocessor operatively coupled to the breaker rating switch and the memory. The microprocessor is configured to interpret a selected circuit breaker rating of the breaker rating switch, set an amplifier gain adjustment for the circuit breaker based on the selected circuit breaker rating, and transmit the selected circuit breaker rating to the memory for storage in the memory. | 06-11-2009 |
Sridhar Devarapalli, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090100500 | Scalable distributed web-based authentication - Web-based authentication includes receiving a packet in a network switch having at least one associative store configured to forward packet traffic to a first one or more processors of the switch that are dedicated to cryptographic processing if a destination port of the packet indicates a secure transport protocol, and to a second one or more processors of the switch that are not dedicated to cryptographic processing if the destination port does not indicate a secure transport protocol. If a source of the packet is an authenticated user, the packet is forwarded via an output port of the switch, based on the associative store. If the source is an unauthenticated user, the packet is forwarded to the first one or more processors if the destination port indicates a secure transport protocol, and to the second one or more processors if the destination port does not indicate a secure transport protocol. | 04-16-2009 |
| 20100325280 | Load Balance Connections Per Server In Multi-Core/Multi-Blade System - A network device includes a plurality of blades, each having a plurality of CPU cores that process requests received by the network device. Each blade further includes an accumulator circuit. Each accumulator circuit periodically aggregates the local counter values of the CPU cores of the corresponding blade. One accumulator circuit is designated as a master, and the other accumulator circuit(s) are designated as slave(s). The slave accumulator circuits transmit their aggregated local counter values to the master accumulator circuit. The master accumulator circuit aggregates the sets of aggregated local counter values to create a set of global counter values. The master accumulator circuit transmits the global counter values to a management processor (for display), to the CPU cores located on its corresponding blade, and to each of the slave accumulator circuits. Each slave accumulator circuit then transmits the global counter values to the CPU cores located on its corresponding blade. | 12-23-2010 |
| 20110010481 | MASSIVE MULTI-CORE PROCESSOR BUILT WITH SERIAL SWITCHING - A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards. | 01-13-2011 |
Sridhar J. Devarapalli, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100254255 | REDUNDANCY SUPPORT FOR NETWORK ADDRESS TRANSLATION (NAT) - Stateful failover redundancy support is provided for network address translation (NAT). A master NAT device is backed-up with at least one back-up NAT device. Existing sessions are synchronized between the two NAT devices, such as via a dedicated link between them. In the event of a failover where the master NAT device is unable to perform its NAT functions, ownership of Internet protocol (IP) addresses is transferred from the master NAT device to the back-up NAT device. The back-up NAT device, which is now owner of the IP addresses, assumes the NAT functionality associated with these IP addresses and continues the existing sessions, as well as processing new sessions. | 10-07-2010 |
Sridhar J. Devarapalli, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120096166 | DOMAIN NAME SYSTEM SECURITY EXTENSIONS (DNSSEC) FOR GLOBAL SERVER LOAD BALANCING - Techniques are provided to enable a network device, such as a switch, to perform global server load balancing (GSLB) while operating as a proxy to a domain name system security extensions (DNSSEC)-capable authoritative DNS server. The network device preserves an original signature generated by the DNSSEC-capable authoritative DNS server for a resource record set contained in a DNSSEC reply. | 04-19-2012 |
Vamsi K. Devarapalli, Albany, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100081281 | Abrasive compositions for chemical mechanical polishing and methods for using same - A colloidal dispersion for chemical mechanical polishing comprising: (a) an abrasive component; and (b) from about 0.05% to about 10% by weight of the abrasive component, a water-soluble amphoteric polymer comprising at least one macromolecular chain B and a part A bonded to a single end of the at least one macromolecular chain B, wherein the macromolecular chain B is derived from one or more ethylenically unsaturated monomers having quaternary ammonium groups or inium groups, and wherein the part A is a polymeric or nonpolymeric group comprising at least one anionic group; wherein the dispersion has a pH of between about 1.5 and about 6. The colloidal dispersion is capable of polishing a substrate comprising silicon nitride and silicon oxide with a reverse selectivity ratio of at least about 27, typically at least 50 the reverse selectivity ratio being the ratio of the rate of removal of the silicon nitride to the rate of removal of the silicon oxide. | 04-01-2010 |
Vijay Devarapalli, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080212478 | Service based bearer control and traffic flow template operation with mobile IP - A method for updating filters, at a Packet Data Serving Node, with a care-of-address associated with at least one of a mobile station or a correspondent node. The method includes the steps of implementing a soft filtering rule at a Packet Data Serving Node and receiving, by the Packet Data Serving Node, a care-of-address that is associated with at least one the mobile station and a correspondent node. The method also includes updating, by the Packet Data Serving Node, filters with the care-of-address to correctly identify flows belonging to a particular session during Mobile IP use. The method further includes filtering, by the Packet Data Serving Node, packets including a care-of-address that is associated with one of the mobile station and the correspondent node. | 09-04-2008 |
Vijay Devarapalli, Los Altos, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120087260 | MODELING RADIO ACCESS NETWORKS - A method, a computer program product and a device, the method is for evaluating a state of a radio access network (RAN), and may include parsing control plane massages that are exchanged between the RAN and a core network that is coupled to the RAN; and determining, by an edge bandwidth manager, a current state of the RAN based on the control plane massages. | 04-12-2012 |