Desineni
Harikishan Desineni, Escondido, CA US
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20080232768 | TECHNIQUES FOR UNIDIRECTIONAL DISABLING OF AUDIO-VIDEO SYNCHRONIZATION - This disclosure describes techniques to allow for unidirectional disabling of audio-video synchronization. In particular, a synchronization command is defined for packet-based network protocols. The synchronization command can disable audio-video synchronization in a sending direction, a receiving direction, or both the sending and receiving direction. In this way, devices are given more control over audio-video synchronization, and can disable such synchronization in a unidirectional manner only, while maintaining synchronization in the opposite direction. | 09-25-2008 |
Harikishan Desineni, San Diego, CA US
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20160111093 | EFFICIENT LOAD SHARING AND ACCELERATING OF AUDIO POST-PROCESSING - Provided are a method and device for audio post-processing. The method may comprise receiving, at a first processor, an audio signal, detecting, at the first processor, a plurality of post-processing modules for altering the audio signal, and creating, based on information identifying functions of the plurality of post-processing modules, an optimized acceleration module. It may further comprise sending, through the optimized acceleration module, a buffer packet of the audio signal along a single data path to a second processor and post-processing, at the second processor, the buffer packet of the audio signal through each of a plurality of associated post-processing modules that correspond to the post-processing modules on the first processor, controlling each associated post-processing module via control paths from each corresponding post-processing module, and receiving, at the first processor, a post-processed buffer packet of the audio signal via a single return data path. | 04-21-2016 |
Rao H. Desineni, Poughkeepsie, NY US
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20090106614 | SYSTEM AND METHOD FOR SIGNATURE-BASED SYSTEMATIC CONDITION DETECTION AND ANALYSIS - Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection. | 04-23-2009 |
20090132976 | METHOD FOR TESTING AN INTEGRATED CIRCUIT AND ANALYZING TEST DATA - A method for testing an integrated circuit and analyzing test data. The method includes: defining a set of signal path selection criteria; selecting a subset of signal paths of an integrated circuit design, the selecting signal paths meeting the selection criteria; identifying pattern observation points for each signal path of the subset of signal paths; selecting a set of features associated with the integrated circuit design; applying a set of test patterns to one or more integrated circuit chips; determining failing signal paths of the subset of signal paths for each integrated circuit chip; mapping failing signal paths of the subset of signal paths to the set of features to generate a correspondence between the failing signal paths and the features; and analyzing the correspondence and identifying suspect features of the set of features based on the analyzing. | 05-21-2009 |
20090240458 | METHOD FOR TESTING INTEGRATED CIRCUITS - A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit. | 09-24-2009 |
20090299679 | Method of Adaptively Selecting Chips for Reducing In-line Testing in a Semiconductor Manufacturing Line - A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs. | 12-03-2009 |
Rao H. Desineni, Essex Junction, VT US
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20110137602 | INSERTION OF FAULTS IN LOGIC MODEL USED IN SIMULATION - A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set. | 06-09-2011 |
Rao H. Desineni, Poughkeepsie IN
Patent application number | Description | Published |
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20110214102 | METHOD FOR TESTING INTEGRATED CIRCUITS - A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit. | 09-01-2011 |