Patent application number | Description | Published |
20080266985 | METHODS AND APPARATUS FOR TESTING INTEGRATED CIRCUITS - In some aspects, a method is provided for testing an integrated circuit (IC). The method includes the steps of selecting a bit from each of a plurality of memory arrays formed on an IC chip, selecting one of the plurality of memory arrays, and storing the selected bit from the selected memory array. Numerous other aspects are provided. | 10-30-2008 |
20090154263 | DESIGN STRUCTURE FOR IMPROVING PERFORMANCE OF SRAM CELLS, SRAM CELL, SRAM ARRAY, AND WRITE CIRCUIT - A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit includes a gate to switch the write circuit on and off. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage. | 06-18-2009 |
20090259977 | Assessing Resources Required to Complete a VLSI Design - A system, method and program product are described in which schematics in a library that a user has tagged are read as ready for layout. The difficulty of each layout is assessed based on statistics indicative of the complexity of the schematic. The statistics may regard the number of connections, pins, devices, and other schematic information. The information is used to calculate the total amount of effort required to complete the design and generate a report. | 10-15-2009 |
20090271669 | High-Speed Testing of Integrated Devices - A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical state from the core to reach an output port of the memory device within an evaluate cycle during a functional operating mode and pass an array built in self test during LBIST mode; enabling the data signal to change from the first logical state to the second logical state during LBIST mode at a time that coincides with the latest possible time the data signal from the core can reach the read output port within the evaluate cycle during the functional operating mode and pass the array built in self test; and executing a logic built-in self test configured to test a logic block located downstream of a transmission path of the memory device. | 10-29-2009 |
20090309644 | METHOD AND APPARATUS TO LIMIT CIRCUIT DELAY DEPENDENCE ON VOLTAGE - The present disclosure is an apparatus for generating a decreasing delay with increasing input voltage to a predetermined voltage value at which point the delay may remain constant. The apparatus may include a circuit comprising a voltage regulator receiving an input voltage and two paths of inverters. At least two paths of inverters may be coupled to an input signal, the input signal may be low voltage (e.g. 0) or high voltage (e.g. 1). A first path may be referenced to a reference voltage while the second path may be referenced to the input voltage. The apparatus may include logic gates for receiving the output of each of the first path of inverters and the output of the second path of inverters to generate a desired output. As the input voltage increases, delay of the apparatus may decrease until the input voltage is approximately the same voltage as the reference voltage, at which the delay may remain constant. | 12-17-2009 |
20100030804 | Synchronization of Locations in Real and Virtual Worlds - Embodiments of the invention provide techniques for synchronizing virtual locations to real locations. In one embodiment, data sources are monitored to detect events that affect real locations. A filter specified by an owner of the virtual location may be used to detect keywords indicating events affecting a particular location. In the event that such events are detected, the owner may be notified to modify the virtual location to match the real location. Optionally, the virtual location may be automatically modified to match the real location. | 02-04-2010 |
20110109366 | Method and Apparatus to Limit Circuit Delay Dependence on Voltage for Single Phase Transition - A delay circuit receives a data input having an input transition and that generates a data output having an output transition. The delay circuit is powered by a voltage source having a voltage. A first delay element is configured to generate a first data signal with a first edge that has a relatively constant delay relative to the input transition irrespective of the voltage of the voltage source. A second delay element is configured to generate a second data signal with a second edge that has a delay relative to the input transition as a function of the voltage of the voltage source. A selection element causes the output transition at the data output to correspond to a latest selected one of the first edge and the second edge. The delay circuit may be employed in a pulse generating circuit. | 05-12-2011 |
20120069688 | IMPLEMENTING SINGLE BIT REDUNDANCY FOR DYNAMIC SRAM CIRCUIT WITH ANY BIT DECODE - A method and a dynamic Static Random Access Memory (SRAM) circuit for implementing single bit redundancy with any bit decode, and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a plurality of bitline columns and a pair of redundancy columns respectively coupled to a respective merged bit column select and redundancy steering multiplexer. Each merged bit column select and redundancy steering multiplexer receives a respective select signal input. A select signal generation circuit receives a redundancy steering signal and a respective one-hot bit select signal, generating the respective select signal input. | 03-22-2012 |
20120147661 | DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY AT POWER-UP - A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by driving the wordlines of all the cells to an activated state. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. In a preferred embodiment, the wordlines are all turned on simultaneously during a power on reset period. Preferably a power on reset signal is used to drive each logic gate of the pre-decoder portion of the address decoder in order to assert all the wordlines. | 06-14-2012 |
20120233576 | SCHEMATIC-BASED LAYOUT MIGRATION - Method, system, computer, etc., embodiments receive an original integrated circuit design into a computerized device. The methods herein automatically replace at least some of the original cells within the original integrated circuit design with replacement cells using the computerized device. Each of the replacement cells has an initial cell size that is unassociated with any specific design size. The methods herein automatically change the original design size of the integrated circuit design to a changed design size, and automatically individually change the initial cell size of each of the replacement cells to different sizes. At least two different replacement cells are changed from the initial cell size by different size reduction amounts based on different amounts of space required within the changed design size for each of the replacement cells. | 09-13-2012 |
20120281457 | Data Dependent SRAM Write Assist - A semiconductor chip has an SRAM (static random access memory). The SRAM includes a data dependent write assist circuit which, on writes, reduces a supply voltage on one of a cross coupled inverter pair in an SRAM cell, thereby making it easier to overcome the one of the cross coupled inverters. | 11-08-2012 |
20130148454 | DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO CLEAR DATA AT POWER-UP - A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. | 06-13-2013 |
20130175631 | LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY - A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell. | 07-11-2013 |
20130222031 | IMPLEMENTING POWER SAVING SELF POWERING DOWN LATCH STRUCTURE - A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal. | 08-29-2013 |
20130235681 | IMPLEMENTING RC AND COUPLING DELAY CORRECTION FOR SRAM - A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals of the SRAM. A precharge pull down device is coupled between the precharge far signal and ground and is controlled responsive to the precharge enable signal to decrease a time delay of the falling transition of the precharge far signal. A respective word line pull up device is coupled between a respective wordline far signal and a voltage supply rail and is controlled responsive to the precharge enable signal to increase wordline voltage level upon a rising transition of the wordline far signal. | 09-12-2013 |
20130258758 | Single Cycle Data Copy for Two-Port SRAM - A static random access memory (SRAM) includes a column of SRAM memory cells. The SRAM may include a circuit to copy a value stored in any SRAM memory cell in a column of SRAM memory cells to any SRAM memory cell in the column of SRAM memory cells in a single cycle of the SRAM. | 10-03-2013 |
20140084980 | MEMORY ARRAY PULSE WIDTH CONTROL - A clock system includes a local clock buffer adapted to receive a variable global clock signal. The local clock buffer produces a first local clock signal from the variable global clock signal. The clock system includes a pulse width logic control circuit in operable communication with the local clock buffer. The pulse width logic control circuit may be adapted to limit the first local clock signal pulse width to be less than the variable global clock signal pulse width during a slow mode. The pulse width logic control circuit may be adapted to expand the first local clock signal pulse width to be greater than the variable global clock signal pulse width during a fast mode. The limited and expanded first local clock signals may signal a local evaluation circuit to address a memory line. | 03-27-2014 |
20140092672 | POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation. | 04-03-2014 |
20140092696 | POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation. | 04-03-2014 |
20140124943 | INTEGRATED DECOUPLING CAPACITOR UTILIZING THROUGH-SILICON VIA - A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region. | 05-08-2014 |
20140126273 | POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a precharge device connected between a voltage supply and the local bit line, and global bit line (GBL) discharge logic connected between a local bit line and a GBL. The GBL discharge logic transfers a logic value of the local bit line to the GBL during a read operation. GBL precharge logic connects the GBL to a global precharge input. The GBL precharge logic is adapted to draw the GBL to a precharge voltage above a discharge voltage and below a supply voltage during a precharge operation. | 05-08-2014 |
20140126276 | POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a precharge device connected between a voltage supply and the local bit line, and global bit line (GBL) discharge logic connected between a local bit line and a GBL. The GBL discharge logic transfers a logic value of the local bit line to the GBL during a read operation. GBL precharge logic connects the GBL to a global precharge input. The GBL precharge logic is adapted to draw the GBL to a precharge voltage above a discharge voltage and below a supply voltage during a precharge operation. | 05-08-2014 |
20140127875 | INTEGRATED DECOUPLING CAPACITOR UTILIZING THROUGH-SILICON VIA - A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region. | 05-08-2014 |
20140149817 | DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY - A semiconductor chip and method for diagnostic testing of combinational logic in a logic and array system including Logic Built in Self Test (LBIST) diagnostics are provided. The semiconductor chip includes a logic and array system, an LBIST system, a clocking module, and an addressing module. The method for diagnostic testing includes providing an initialization pattern to an array in the logic and array system, applying a diagnostic control setup, and running the diagnostic test. The diagnostic control setup includes firing a clock every diagnostic test clock cycle and selecting an address from a subset of an address space. | 05-29-2014 |
20140149818 | DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY - A semiconductor chip and method for diagnostic testing of combinational logic in a logic and array system including Logic Built in Self Test (LBIST) diagnostics are provided. The semiconductor chip includes a logic and array system, an LBIST system, a clocking module, and an addressing module. The method for diagnostic testing includes providing an initialization pattern to an array in the logic and array system, applying a diagnostic control setup, and running the diagnostic test. The diagnostic control setup includes firing a clock every diagnostic test clock cycle and selecting an address from a subset of an address space. | 05-29-2014 |
20140169076 | POWER MANAGEMENT SRAM WRITE BIT LINE DRIVE CIRCUIT - A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, where the downlevel is a second supply voltage lower than the first supply voltage. | 06-19-2014 |
20140293679 | MANAGEMENT OF SRAM INITIALIZATION - An embodiment of the current disclosure is directed to a Static Random Access Memory (SRAM) device, and a design structure for the SRAM device. The SRAM device may include one or more SRAM cells. Each SRAM cell may further include a first and a second CMOS inverter that are cross-coupled. The first and second CMOS inverters may each have a first switch and a second switch. The SRAM device may also include a reset circuit. The reset circuit may be coupled to a first node of the first switch of the first CMOS inverter. The reset circuit may drive the first CMOS inverter to output a logical high signal in a reset mode. | 10-02-2014 |
20140353764 | LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY - A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell. | 12-04-2014 |