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Derenge
Charles L. Derenge, Phoenix, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20080294749 | SYSTEM AND METHOD FOR GLOBALLY SHARING FMS DATA OR OTHER FILES FROM AERIAL PLATFORMS OR OTHER SOURCES ANYWHERE IN THE WORLD - A system for globally sharing data or files from aerial platforms or other sources located anywhere in the world may include a satellite modem to transfer data to a satellite system for globally sharing data or files. The system may also include a data flow controller to control a flow of data to the satellite modem from at least one of an aerial platform and a data source, located anywhere in the world. | 11-27-2008 |
Michael A. Derenge, Columbia, MD US
| Patent application number | Description | Published |
|---|---|---|
| 20100171124 | Low-defect density gallium nitride semiconductor structures and fabrication methods - A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer. | 07-08-2010 |
Michael Andrew Derenge, Columbia, MD US
| Patent application number | Description | Published |
|---|---|---|
| 20090233414 | Method for fabricating group III-nitride high electron mobility transistors (HEMTs) - A method of manufacturing a transistor comprises providing a wafer; growing a group III-nitride semiconductor material on a first side of the wafer; creating alignment marks on a second side of the wafer, the second side of the wafer being positioned opposite to the first side of the wafer; etching the first side of the wafer to create free standing walls on the first side of the wafer; growing pendeo-epitaxy regrowth regions on the free standing walls; and forming mesa isolated regions in the pendeo-epitaxy regrowth regions. The method may further comprise positioning a patterned mask on the first side of the wafer; and aligning the patterned mask with the alignment marks located on the second side of the wafer. | 09-17-2009 |
| 20100133656 | Method Using Multiple Layer Annealing Cap for Fabricating Group III-Nitride Semiconductor Device Structures and Devices Formed Thereby - A method of preventing the escape of nitrogen during the activation of ion implanted dopants in a Group III-nitride semiconductor compound without damaging the Group III-nitride semiconductor comprising: depositing a first layer of another Group III-nitride that acts as an adhesion layer; depositing a second layer of a Group III-nitride that acts as a mechanical supporting layer; said first and second layers forming an annealing cap to prevent the escape of the nitrogen component of the Group III-nitride semiconductor; annealing the Group III-nitride semiconductor at a temperature in the range of approximately 1100-1250° C.; and removing the first and second layers from the Group III-nitride semiconductor. | 06-03-2010 |