Patent application number | Description | Published |
20100072569 | Method of forming an isolation layer, method of manufacturing a semiconductor device using the same, and semiconductor device having an isolation layer - In a method of forming an isolation layer, a plurality of trenches is formed on a substrate. A liner is formed on inner walls of the trenches. The liner is thermally oxidized to fill up some of the trenches. The other trenches are filled up with an insulation material. As a result, the isolation layer is free of voids. | 03-25-2010 |
20100203700 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes preparing a substrate having a recessed area. A silicon oxide layer is formed at the recessed area. A catalytic nitridation treatment is performed for an upper portion of the silicon oxide layer to form a nitridation reactant on the upper portion of the silicon oxide layer. A dielectric layer is formed on the silicon oxide layer where the nitridation reactant is formed. The dielectric layer is annealed. According to the foregoing method, recession of the dielectric layer is prevented to fabricate a high-quality semiconductor device. | 08-12-2010 |
20110316168 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure. | 12-29-2011 |
20110318922 | METHOD OF FORMING SEMICONDUCTOR DEVICE - The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern. | 12-29-2011 |
20110318923 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME INCLUDING A CONDUCTIVE STRUCTURE IS FORMED THROUGH AT LEAST ONE DIELECTRIC LAYER AFTER FORMING A VIA STRUCTURE - For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized. | 12-29-2011 |
20120039564 | Photoelectric Integrated Circuit Devices And Methods Of Forming The Same - A photoelectric integrated circuit device may include a substrate including an electronic device region and an on die optical input/output device region, the substrate having a trench in the on die optical input/output device region; a lower clad layer provided in the trench, the lower clad layer having an upper surface lower than a surface of the substrate; a core provided on the lower clad layer; an insulating pattern provided on the core; an optical detection pattern provided on the insulating pattern, the optical detection pattern having at least a portion provided in the trench; and at least one transistor provided on the substrate of the electronic device region. | 02-16-2012 |
20120043666 | Semiconductor Device and Method of Fabricating the Same - For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized. | 02-23-2012 |
20120058647 | OXIDATION-PROMOTING COMPOSITIONS, METHODS OF FORMING OXIDE LAYERS, AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES - Provided according to embodiments of the present invention are an oxidation-promoting compositions, methods of forming oxide layers, and methods of fabricating semiconductor devices. In some embodiments of the invention, the oxidation-promoting composition includes an oxidation-promoting agent having a structure of A-M-L, wherein L is a functional group that is chemisorbed to a surface of silicon, silicon oxide, silicon nitride, or metal, A is a thermally decomposable oxidizing functional group, and M is a moiety that allows A and L to be covalently bonded to each other. | 03-08-2012 |
20120119376 | SEMICONDUCTOR CHIPS AND METHODS OF FORMING THE SAME - Provided are a semiconductor chip and a method of manufacturing the same. The semiconductor chip includes a substrate having a first side and a second side facing each other, and a through electrode being disposed in a hole penetrating the substrate, wherein an opening surrounded by the through electrode is disposed in the hole, wherein the opening comprises a first end adjacent to the first side of the substrate and a second end adjacent to the second side of the substrate | 05-17-2012 |
20120132986 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a plurality of horizontal channel transistors formed thereon, an insulation layer structure on the substrate and covering the horizontal transistors, and a plurality of vertical channel transistors on the insulation layer structure. | 05-31-2012 |
20120142185 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - In methods of manufacturing a semiconductor device, a substrate having a first surface and a second surface opposite to the first surface is prepared. A sacrificial layer pattern is formed in a region of the substrate that a through electrode will be formed. The sacrificial layer pattern extends from the first surface of the substrate in a thickness direction of the substrate. An upper wiring layer is formed on the first surface of the substrate. The upper wiring layer includes a wiring on the sacrificial layer pattern. The second surface of the substrate is partially removed to expose the sacrificial layer pattern. The sacrificial layer pattern is removed from the second surface of the substrate to form an opening that exposes the wiring. A through electrode is formed in the opening to be electrically connected to the wiring. | 06-07-2012 |
20120282736 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING THE SAME - In a method of manufacturing a semiconductor device, a front end of line (FEOL) process may be performed on a semiconductor substrate to form a semiconductor structure. A back end of line (BEOL) process may be performed on the semiconductor substrate to form a wiring structure electrically connected to the semiconductor structure, thereby formed a semiconductor chip. A hole may be formed through a part of the semiconductor chip. A preliminary plug may have a dimple in the hole. The preliminary plug may be expanded into the dimple by a thermal treatment process to form a plug. Thus, the plug may not have a protrusion protruding from the upper surface of the semiconductor chip, so that the plug may be formed by the single CMP process. | 11-08-2012 |
20130187287 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes a circuit pattern over a first surface of a substrate, an insulating interlayer covering the circuit pattern, a TSV structure filling a via hole through the insulating interlayer and the substrate, an insulation layer structure on an inner wall of the via hole and on a top surface of the insulating interlayer, a buffer layer on the TSV structure and the insulation layer structure, a conductive structure through the insulation layer structure and a portion of the insulating interlayer to be electrically connected to the circuit pattern, a contact pad onto a bottom of the TSV structure, and a protective layer structure on a second surface the substrate to surround the contact pad. | 07-25-2013 |
20130337647 | METHODS OF FORMING A SEMICONDUCTOR DEVICE - The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern. | 12-19-2013 |
20130344695 | SEMICONDUCTOR CHIPS AND METHODS OF FORMING THE SAME - Provided are a semiconductor chip and a method of manufacturing the same. The semiconductor chip includes a substrate having a first side and a second side facing each other, and a through electrode being disposed in a hole penetrating the substrate, wherein an opening surrounded by the through electrode is disposed in the hole, wherein the opening comprises a first end adjacent to the first side of the substrate and a second end adjacent to the second side of the substrate | 12-26-2013 |
20140035144 | Semiconductor Devices Having Through Electrodes and Methods of Fabricating the Same - Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate. | 02-06-2014 |
20140035164 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure. | 02-06-2014 |
20140179103 | SEMICONDUCTOR DEVICES HAVING THROUGH-VIAS AND METHODS FOR FABRICATING THE SAME - A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed. | 06-26-2014 |
20140199810 | Methods for Forming Semiconductor Devices Using Sacrificial Layers - A fabricating method for a semiconductor device is provided. The fabricating method includes providing a first wafer, forming a sacrificial layer on the first wafer, forming a release layer on the sacrificial layer, forming an adhesive layer on the release layer, and placing a second wafer on the adhesive layer and bonding the first wafer to the second wafer. | 07-17-2014 |
20140327150 | SEMICONDUCTOR PACKAGES, METHODS OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE STRUCTURES INCLUDING THE SAME - A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer. | 11-06-2014 |