| Patent application number | Description | Published |
|---|
| 20080252504 | METHOD OF COMPENSATING CHANNEL OFFSET VOLTAGE FOR COLUMN DRIVER AND COLUMN DRIVER FOR LCD IMPLEMENTED THEREOF - A technique for removing vertical stripe artifacts generated in a Liquid Crystal Display (LCD) panel, more particularly a technique for compensating for and removing an inter-channel offset voltage of a column driver, which causes the vertical stripe artifacts, is disclosed. An offset voltage generated in each channel for driving each pixel of the LCD panel is detected for a whole signal path and offset voltages detected for all channels are compared and extracted according to a given timing sequence by a common signal comparator, thereby preventing the offset of the detection comparator and reducing a chip size of the column driver in contrary to the prior art. Moreover, an inter-channel offset voltage is detected in a digital circuit mode, thereby compensating for process variations in a semiconductor chip manufacturing process in circuit terms. | 10-16-2008 |
| 20090219739 | Range-Matching Cell and Content Addressable Memories Using the Same - A range-matching cell (RMC) includes bit lines (BL); a word line (WL); a match line (ML); search lines (SL); a memory cell ( | 09-03-2009 |
| 20090313410 | BI-DIRECTIONAL MULTI-DROP BUS MEMORY SYSTEM - A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs. | 12-17-2009 |
| 20100134165 | TIME-TO-DIGITAL CONVERTER AND ALL-DIGITAL PHASE-LOCKED LOOP - A time-to-digital converter (TDC) includes a converter which receives a first signal and a second signal, delays the second signal in phases using a plurality of delay elements which are coupled in series, compares the delayed second signal with the first signal, and outputs a phase error of the second signal with respect to the first signal, a phase frequency detector which receives the first signal, and a third signal from one of the nodes in the plurality of delay elements, and outputs a phase difference between the first signal and the third signal, and a frequency detector which outputs a frequency error of the second signal with respect to the first signal as a digital code using an output signal of the phase frequency detector and the second signal. | 06-03-2010 |
| 20100156550 | ADJUSTABLE CAPACITOR, DIGITALLY CONTROLLED OSCILLATOR, AND ALL-DIGITAL PHASE LOCKED LOOP - An adjustable capacitor is provided including a capacitor unit including a plurality of capacitor groups aligned in a matrix format and a switch unit to adjust capacitance by connecting the plurality of capacitor groups in parallel according to a selection signal of a column and row of the matrix. Accordingly, the adjustable capacitor may be realized of a small size but with a high capacitance change rate. | 06-24-2010 |
| 20100238157 | METHOD OF MODULATING/DEMODULATING A SIGNAL, APPARATUS FOR PERFORMING THE METHOD AND DISPLAY APPARATUS HAVING THE APPARATUS - A method of modulating and demodulating a signal includes modulating data information included in an input data signal provided from an external source and clock information included in an input clock signal provided from the external source into a transmission signal, using (n+1) delay clock signals generated based on the input clock signal, where n is a natural number. The transmission signal is demodulated into an output clock signal including restored clock information and an output data signal including restored data information, using (m+1) delay clock signals generated based on the clock information, where m is a natural number less than n. | 09-23-2010 |
| 20110022890 | CLOCK AND DATA RECOVERY CIRCUIT WITH ELIMINATING DATA-DEPENDENT JITTERS - The present invention relates to a clock and data recovery circuit (CDR), and in particular, to a CDR circuit in a full digital scheme which cancels the data-dependent jitter. A DDJ cancellation circuit according to the present invention efficiently cancels the data-dependent jitter, making it possible to configure the reliable clock and data recovery circuit in the serial link data communication through the channel of the predetermined bandwidth. | 01-27-2011 |
| 20110267122 | ALL-DIGITAL CLOCK DATA RECOVERY DEVICE AND TRANSCEIVER IMPLEMENTED THEREOF - The present invention relates to an all-digital clock data recovery (CDR) which is implemented by a digital filter and a digitally controlled oscillator. The CDR of the present invention comprises a phase detector producing a digital sequence of data and a digital sequence of edge by sampling the serial data stream with a clock, a de-serializer transforming the digital sequences of data and edge into n-bit bus, a digitally controlled oscillator (DCO) implemented by a multi-stage chain of inverters having a variable resistance switching matrix wherein the resistance of each element of the variable resistance switching matrix is varied in such a way that the supply current being fed to each inverter is controlled in pursuant to a digital control code, and thereby producing a clock whose oscillation frequency is updated and fed to the phase detector, a digital synthesis control logic circuit generating a thermometer-code-type digital control code out of the n-bit data and n-bit edge from the de-serializer wherein the thermometer-code-type digital control code is fed to the DCO, and a 2-bit direct forward path directly controlling the frequency of the clock being produced by the DCO with an operating speed which is faster than the digital synthesis control logic circuit by n times. | 11-03-2011 |
