Denorme

Laurence Denorme, Isnes BE

Patent application number	Description	Published
20090162833	TEST DEVICE FOR RAPID DIAGNOSTICS - Devices for detecting analytes or analogues thereof in a biological sample are disclosed. The device includes a solid support. The solid support has several juxtaposed zones. The sample is able to migrate from a sample receiving zone towards a detection zone. The analyte, if present, is detected in the detection zone. Both zones have material allowing a capillary flow of the sample through the zones. In between the zones, there is an intermediate zone of transport of the sample which is free from any capillary material. This allows the ample to migrate by gravitational forces on the support laid in a vertical position. Methods for detecting analytes or analogues thereof in a biological sample using the device are also disclosed.	06-25-2009

Patent application number	Description	Published
20110147881	HYBRID SUBSTRATE WITH IMPROVED ISOLATION AND SIMPLIFIED METHOD FOR PRODUCING A HYBRID SUBSTRATE - A hybrid substrate comprises first and second active areas made from semiconductor materials laterally offset from one another and separated by an isolation area. The main surfaces of the isolation area and of the first active area form a plane. The hybrid substrate is obtained from a source substrate successively comprising layers made from a first and second semiconductor materials separated by an isolation layer. A single etching mask is used to pattern the isolation area, first active area and second active area. The main surface of the first active area is released thereby forming voids in the source substrate. The etching mask is eliminated above the first active area. A first isolation material is deposited, planarized and etched until the main surface of the first active area is released.	06-23-2011

Patent application number	Description	Published
20110014769	MANUFACTURING METHOD FOR PLANAR INDEPENDENT-GATE OR GATE-ALL-AROUND TRANSISTORS - The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.	01-20-2011