| Patent application number | Description | Published |
|---|
| 20080245862 | SYSTEM AND METHOD FOR INTERACTIVE MARKETING TO CONSUMERS - A system and method for interactive marketing to consumers and, more particularly, to a system and method for marketing merchandise to consumers in an interactive retail environment. The method includes detecting a disturbance in an area and sending information related to the disturbance to a back end merchandising system. The method further includes retrieving relevant information related to the detected disturbance from the back end merchandising system and displaying the relevant information on a display surface. | 10-09-2008 |
| 20090058647 | SYSTEM AND METHOD FOR RFID DYNAMIC CONTENT PRESENTATION - A system and method for providing RFID dynamic content presentation using wireless devices and RFID technologies. The method comprises providing a wireless capable device which is configured to receive RFID information and store the RFID information in storage for later retrieval. The system is an infrastructure which comprises at least one RFID tag which stores RFID information; and a wireless capable device which is configured to receive the RFID information and store the RFID information in storage for later retrieval. | 03-05-2009 |
| 20090063705 | SYSTEM AND METHOD OF SENDING COMPRESSED HTML MESSAGES OVER TELEPHONY PROTOCOL - A system and method for sending compressed html messages and, more particularly, a system and method for sending compressed html messages over a telephony protocol. the method comprises compressing an html message and sending the compressed html message via a telephony protocol. The compressed html message is sent as an SMS message and the telephony protocol is SS7 protocol, bypassing TCP/IP. The compressed html message can be coded with a return number, forcing a return message to be sent via a text message over SS7 protocol. The system and method includes a computer infrastructure operable to compress an html message and send the compressed html message such as and SMS message via a telephony protocol. A computer program product comprising a computer usable medium having readable program code embodied in the medium for performing the processes is also contemplated. | 03-05-2009 |
| 20100075610 | SYSTEM AND METHOD FOR REDUCING LATENCY OF LOCATION BASED INFORMATION RETRIEVED FROM A LOCATION SERVICE - A system and method is provided for reducing latency when providing user location information services. The system is implemented in a computer infrastructure which comprises computer executable code tangibly embodied on a computer readable medium. The executable code is operable to trigger a location based service to obtain user location information prior to the user registering for location services. | 03-25-2010 |
| 20110131078 | SYSTEM AND METHOD TO MODEL AND FORECAST TECHNOLOGY ADOPTION - A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to at least one of receive and assess current technology adoption trends. Additionally, the programming instructions are operable to provide a technology adoption forecast. | 06-02-2011 |
| 20120223815 | SYSTEM AND METHOD FOR RFID DYNAMIC CONTENT PRESENTATION - A system and method for providing RFID dynamic content presentation using wireless devices and RFID technologies. The method comprises providing a wireless capable device which is configured to receive RFID information and store the RFID information in storage for later retrieval. The system is an infrastructure which comprises at least one RFID tag which stores RFID information; and a wireless capable device which is configured to receive the RFID information and store the RFID information in storage for later retrieval. | 09-06-2012 |
| Patent application number | Description | Published |
|---|
| 20110073961 | SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE - A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor. | 03-31-2011 |
| 20110108943 | HYBRID DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH ENHANCED MOBILITY CHANNELS - A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive back gate layer formed on the lower insulating layer; an upper insulating layer formed on the back gate layer; and a hybrid semiconductor-on-insulator layer formed on the upper insulating layer, the hybrid semiconductor-on-insulator layer comprising a first portion having a first crystal orientation and a second portion having a second crystal orientation. | 05-12-2011 |
| 20110115021 | ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATHIN BOX - Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion. | 05-19-2011 |
| 20110115553 | SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE - SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection. | 05-19-2011 |
| 20110121811 | POWER DELIVERY IN A HETEROGENEOUS 3-D STACKED APPARATUS - A heterogeneous three-dimensional (3-D) stacked apparatus is provided that includes multiple layers arranged in a stacked configuration with a lower layer configured to receive a board-level voltage and one or more upper layers stacked above the lower layer. The heterogeneous 3-D stacked apparatus also includes multiple tiles per layer, where each tile is designed to receive a separately regulated voltage. The heterogeneous 3-D stacked apparatus additionally includes at least one layer in the one or more upper layers with voltage converters providing the separately regulated voltage converted from the board-level voltage. | 05-26-2011 |
| 20120168864 | SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE - A transistor device includes a patterned gate structure formed over a substrate, the patterned gate structure including a gate conductor, a gate dielectric layer and sidewall spacers; and a doped well implant formed in the substrate, the well implant being self-aligned with the patterned gate structure. | 07-05-2012 |
| 20120284541 | POWER DELIVERY IN A HETEROGENEOUS 3-D STACKED APPARATUS - A heterogeneous three-dimensional (3-D) stacked apparatus is provided that includes multiple layers arranged in a stacked configuration with a lower layer configured to receive a board-level voltage and one or more upper layers stacked above the lower layer. The heterogeneous 3-D stacked apparatus also includes multiple tiles per layer, where each tile is designed to receive a separately regulated voltage. The heterogeneous 3-D stacked apparatus additionally includes at least one layer in the one or more upper layers with voltage converters providing the separately regulated voltage converted from the board-level voltage. | 11-08-2012 |
