| Patent application number | Description | Published |
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| 20090222603 | BUS COMMUNICATION SYSTEM - The invention relates to a bus communication system for serialized data transmission comprising: a transmitter, a receiver, and a data line, whereby said transmitter is arranged for transmitting a data signal over said data line; said receiver is arranged for receiving said data signal from said data line, wherein said transmitter is arranged for transmitting an end of transmission signal over said data line after transmission of said data signal is completed; and said receiver is arranged for receiving said end of transmission signal from said data line. | 09-03-2009 |
| 20100067633 | FAST POWERING-UP OF DATA COMMUNICATION SYSTEM - A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up. | 03-18-2010 |
| 20100085093 | MULTI-PHASE CLOCK SYSTEM - The invention relates to multi-phase clock system for receiving a plurality of clock signals (CLK | 04-08-2010 |
| 20100091921 | FAST POWERING-UP OF DATA COMMUICATION SYSTEM - A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up. | 04-15-2010 |
| 20100232304 | Mode switching of a data communications link - A method and apparatus for determining a time-out period used for switching between a first operational mode and a second operational mode of a data communications link, comprising detecting a signal used to request switching from the first operational mode to the second operational mode; measuring the duration of the signal; and determining the time-out period in dependence on the measured duration of the signal. | 09-16-2010 |
| Patent application number | Description | Published |
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| 20080279225 | Synchronized Receiver - There is provided a method of operating a communications system comprising a transmitting station and a receiving station, the method in the transmitting station comprising encoding a clock signal with data to form encoded signals for transmission; transmitting the encoded signals to the receiving station; the method in the receiving station comprising decoding the encoded signals to extract the clock signal and data; processing the data under the control of the decoded clock signal. The method further comprises, when no data is required to be transmitted to the receiving station, transmitting further encoded signals to the receiving station in order for the receiving station to decode the further encoded signals and extract a clock signal. | 11-13-2008 |
| 20080313375 | Bus Station and System and Method of Maintaining Synchronizing of a Bus Station - A bus station circuit ( | 12-18-2008 |
| 20090219983 | DATA COMMUNICATION CIRCUIT WITH EQUALIZATION CONTROL - An adaptive equalizer comprises an adjustable equalizer circuit that allows to enhance the frequency dependence of contents of the transmitted signals which suffer from losses in the connected transmission channel. A blind equalization tuning procedure is proposed that operates without knowledge about the characteristic of transmission channel. Phase positions of transitions in the equalized signal are detected. A digital post-processing circuit evaluates a measure for spread of the detected phase positions of transitions, accumulated over a plurality of the symbol periods. The digital post-processing circuit controls the adjustable equalizer, setting the adjustable equalizer to a setting wherein the detected spread is minimized. | 09-03-2009 |
| 20100172457 | METHOD AND CIRCUIT FOR RECEIVING DATA - The invention relates to a circuit and method for receiving a signal of which—at the receiver end—the frequency is basically unknown. By sampling the data and deriving the frequency of the signal (or actually: the data rate of the data carried by the signal) and setting a phase locked loop in the receiver to the derived—estimated—circuit, the receiver can very quickly tune in to the frequency of the signal. Hence, no embedded or accompanying clock is required for the signal. Oversampling of the signal by the receiver front end is preferred, though. | 07-08-2010 |
| 20100260283 | DUTY-CYCLE MODULATED TRANSMISSION - A duty-cycle modulated bit signalling method and circuit, comprising: signaling bits by virtue of a duty-cycle ratio; wherein the duty-cycle ratio is varied dependent upon the transmission rate of the signalling. A bit period comprises a long phase and a short phase and the duty-cycle therebetween is varied such that the ratio between the duration of the long phase and the duration of the short phase is increased for decreasing transmission rate. The duty-cycle ratio is varied dependent upon the transmission rate of the signalling according to one or more ranges of transmission rate. In a higher transmission rate range the duty-cycle is defined as a fixed ratio, and in a lower transmission range the duty-cycle is defined by a fixed length of the short phase of the bit period. | 10-14-2010 |
| 20110025382 | FREQUENCY DIVIDER - A frequency divider ( | 02-03-2011 |
| 20120119821 | INTEGRATED CIRCUIT FOR EMULATING A RESISTOR - An integrated circuit for emulating a resistor is based on the output resistance of a non-linear circuit element, such as a transistor. In the case of a transistor, it is biased into operation in its linear region, and a voltage dependent on the ac source-drain voltage is coupled to the gate voltage, thereby to improve linearity of the drain-source resistance with respect to the drain-source voltage. This modification to the gate voltage can be used to alter the transfer function such that the drain-source resistance is no longer dependent on the drain-source voltage. | 05-17-2012 |
