Patent application number | Description | Published |
20110072235 | EFFICIENT MEMORY TRANSLATOR WITH VARIABLE SIZE CACHE LINE COVERAGE - One embodiment of the present invention sets forth a system and method for supporting high-throughput virtual to physical address translation using compressed TLB cache lines with variable address range coverage. The amount of memory covered by a TLB cache line depends on the page size and page table entry (PTE) compression level. When a TLB miss occurs, a cache line is allocated with an assumed address range that may be larger or smaller than the address range of the PTE data actually returned. Subsequent requests that hit a cache line with a fill pending are queued until the fill completes. When the fill completes, the cache line's address range is set to the address range of the PTE data returned. Queued requests are replayed and any that fall outside the actual address range are reissued, potentially generating additional misses and fills. | 03-24-2011 |
20140122829 | EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS - A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches. | 05-01-2014 |
20140123145 | EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS - A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches. | 05-01-2014 |
20140123146 | EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS - A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches. | 05-01-2014 |
20140267334 | CPU-TO-GPU AND GPU-TO-GPU ATOMICS - One embodiment of the present invention includes techniques for a first processing unit to perform an atomic operation on a memory page shared with a second processing unit. The memory page is associated with a page table entry corresponding to the first processing unit. Before executing the atomic operation, an MMU included in the first processing unit evaluates an atomic permission bit that is included in the page table entry. If the MMU determines that the atomic permission bit is inactive, then the two processing units coordinate to change the permission status of the memory page. As part of the status change, the atomic permission bit in the page table entry is activated. Subsequently, the first processing unit performs the atomic operation uninterrupted by the second processing unit. Advantageously, coordinating the processing unit via the atomic permission bit ensures the proper and efficient execution of the atomic operation. | 09-18-2014 |
20140281110 | PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM - Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter. | 09-18-2014 |
20140281255 | PAGE STATE DIRECTORY FOR MANAGING UNIFIED VIRTUAL MEMORY - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281256 | FAULT BUFFER FOR RESOLVING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281263 | REPLAYING MEMORY TRANSACTIONS WHILE RESOLVING MEMORY ACCESS FAULTS - One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved. | 09-18-2014 |
20140281264 | MIGRATION COUNTERS FOR HYBRID MEMORIES IN A UNIFIED VIRTUAL MEMORY SYSTEM - Embodiments of the approaches disclosed herein include a subsystem that includes an access tracking mechanism configured to monitor access operations directed to a first memory and a second memory. The access tracking mechanism detects an access operation generated by a processor for accessing a first memory page residing on the second memory. The access tracking mechanism further determines that the first memory page is included in a first subset of memory pages residing on the second memory. The access tracking mechanism further locates, within a reference vector, a reference bit that corresponds to the first memory page, and sets the reference bit. One advantage of the present invention is that memory pages in a hybrid system migrate as needed to increase overall memory performance. | 09-18-2014 |
20140281296 | FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281299 | OPPORTUNISTIC MIGRATION OF MEMORY PAGES IN A UNIFIED VIRTUAL MEMORY SYSTEM - Techniques are disclosed for transitioning a memory page between memories in a virtual memory subsystem. A unified virtual memory (UVM) driver detects a page fault in response to a memory access request associated with a first memory page, where a local page table does not include an entry corresponding to a virtual memory address included in the memory access request. The UVM driver, in response to the page fault, executes a page fault sequence. The page fault sequence includes modifying the ownership state associated with the first memory page to be central-processing-unit-shared. The page fault sequence further includes scheduling the first memory page for migration from a system memory associated with a central processing unit (CPU) to a local memory associated with a parallel processing unit (PPU). One advantage of the disclosed approach is that the PPU accesses memory pages with greater efficiency. | 09-18-2014 |
20140281319 | SYSTEM AND METHOD FOR PROTECTING DATA - A system and method are provided for protecting data. In operation, a request to read data from memory is received. Additionally, it is determined whether the data is stored in a predetermined portion of the memory. If it is determined that the data is stored in the predetermined portion of the memory, the data and a protect signal are returned for use in protecting the data. In certain embodiments of the invention, data stored in the predetermined portion of the memory may be further processed and written hack to the predetermined portion of the memory. In other embodiments of the invention, such processing may involve unprotected data stored outside the predetermined portion of the memory. | 09-18-2014 |
20140281324 | MIGRATING PAGES OF DIFFERENT SIZES BETWEEN HETEROGENEOUS PROCESSORS - One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history. | 09-18-2014 |
20140281356 | MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT - One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased. | 09-18-2014 |
20140281357 | COMMON POINTERS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281358 | MIGRATION SCHEME FOR UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281364 | MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT - One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased. | 09-18-2014 |
20140281365 | FRAME BUFFER ACCESS TRACKING VIA A SLIDING WINDOW IN A UNIFIED VIRTUAL MEMORY SYSTEM - One embodiment of the present invention is a memory subsystem that includes a sliding window tracker that tracks memory accesses associated with a sliding window of memory page groups. When the sliding window tracker detects an access operation associated with a memory page group within the sliding window, the sliding window tracker sets a reference bit that is associated with the memory page group and is included in a reference vector that represents accesses to the memory page groups within the sliding window. Based on the values of the reference bits, the sliding window tracker causes the selection a memory page in a memory page group that has fallen into disuse from a first memory to a second memory. Because the sliding window tracker tunes the memory pages that are resident in the first memory to reflect memory access patterns, the overall performance of the memory subsystem is improved. | 09-18-2014 |
20150082001 | TECHNIQUES FOR SUPPORTING FOR DEMAND PAGING - One embodiment of the present invention includes techniques to support demand paging across a processing unit. Before a host unit transmits a command to an engine that does not tolerate page faults, the host unit ensures that the virtual memory addresses associated with the command are appropriately mapped to physical memory addresses. In particular, if the virtual memory addresses are not appropriately mapped, then the processing unit performs actions to map the virtual memory address to appropriate locations in physical memory. Further, the processing unit ensures that the access permissions required for successful execution of the command are established. Because the virtual memory address mappings associated with the command are valid when the engine receives the command, the engine does not encounter page faults upon executing the command. Consequently, in contrast to prior-art techniques, the engine supports demand paging regardless of whether the engine is involved in remedying page faults. | 03-19-2015 |
20150097847 | MANAGING MEMORY REGIONS TO SUPPORT SPARSE MAPPINGS - One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management. | 04-09-2015 |
20150199280 | METHOD AND SYSTEM FOR IMPLEMENTING MULTI-STAGE TRANSLATION OF VIRTUAL ADDRESSES - A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory. | 07-16-2015 |
Patent application number | Description | Published |
20140369375 | BOAT AND COIL DESIGNS - Disclosed are vessels used for melting material to be injection molded to form a part. One vessel has a body formed from a plurality of elongate segments configured to be electrically isolated from each other and with a melting portion for melting meltable material therein. Material can be provided between adjacent segments. An induction coil can be used to melt the material in the body. Other vessels have a body with an embedded induction coil therein. The embedded coil can be configured to surround the melting portion, or can be positioned below and/or adjacent the melting portion, so that meltable material is melted. The vessels can be used to melt amorphous alloys, for example. | 12-18-2014 |
20150144292 | CONTAINMENT GATE FOR INLINE TEMPERATURE CONTROL MELTING - Disclosed is an apparatus comprising at least one gate and a vessel, the gate being configured to move between a first position to restrict entry into an ejection path of the vessel and contain a material in a meltable form within the vessel during melting of the material, and a second position to allow movement of the material in a molten form through the ejection path. The gate can move linearly or rotate between its first and second positions, for example. The apparatus is configured to melt the material and the at least one gate is configured to allow the apparatus to be maintained under vacuum during the melting of the material. Melting can be performed using an induction source. The apparatus may also include a mold configured to receive molten material and for molding a molded part, such as a bulk amorphous alloy part. | 05-28-2015 |
20160067766 | 3D PRINTED INVESTMENT MOLDS FOR CASTING OF AMORPHOUS ALLOYS AND METHOD OF USING SAME - Described herein is a method of forming a 3D investment mold using a layer-by-layer construction (3D printing). The mold is configured for receipt of a molten alloy having a composition configured to form a bulk metallic glass (BMG) on cooling. The mold has a hollow interior between inner and outer walls. The hollow interior receives the molten alloy for molding it between the inner and outer walls of the mold. A method of casting using the 3D investment mold is also disclosed, which may include filling the mold with molten alloy, removing bubbles, quenching the molten alloy in the mold, and then removing the mold. | 03-10-2016 |
20160089715 | HORIZONTAL SKULL MELT SHOT SLEEVE - Disclosed are embodiments of a vessel configured to contain a secondary magnetic induction field therein for melting materials, and methods of use thereof. The vessel can be used in an injection molding apparatus having an induction coil positioned adjacent to the vessel. The vessel can have a tubular body configured to substantially surround and receive a plunger tip. Longitudinal slots or gaps extend through the thickness of the body to allow and/or direct eddy currents into the vessel during application of an RF induction field from the coil. The body also includes temperature regulating lines configured to flow a liquid within. The temperature regulating lines can be provided to run longitudinally within the wall(s) of the body between its inner bore and outer surface(s). A flange may be provided at one end of the body to secure the body within an injection molding apparatus. | 03-31-2016 |
20160091250 | QUARTZ POURING & CASTING SYSTEM FOR NON-WETTING AMORPHOUS ALLOYS - Described herein is a crucible with a rod fused thereon to optimize pouring of molten material, and method of using the same. The crucible has a body configured for receipt of an amorphous alloy material in a vertical direction, and the rod extends in a horizontal direction from the body. The body of the crucible and the rod are formed from silica or quartz. The rod may be fused to the body of the crucible and provided off a center axis so that pouring molten material is improved when the crucible is rotated. | 03-31-2016 |
Patent application number | Description | Published |
20080276785 | Constant force scoring device and method for using same - A scoring device is described herein that applies a constant force while scoring a piece of material so that there is a consistent score quality (or vent depth) within the scored piece of material. In one embodiment, the piece of material is a bowed shaped glass sheet that is supported by a conformable nosing device which has been configured to have a bowed shape that substantially matches the bowed shape of the glass sheet. | 11-13-2008 |
20120006058 | CONSTANT FORCE SCORING DEVICE AND METHOD FOR USING SAME - A scoring device is described herein that applies a constant force while scoring a piece of material so that there is a consistent score quality (or vent depth) within the scored piece of material. In one embodiment, the piece of material is a bowed shaped glass sheet that is supported by a conformable nosing device which has been configured to have a bowed shape that substantially matches the bowed shape of the glass sheet. | 01-12-2012 |
20120297828 | GLASS MOLDING SYSTEM AND RELATED APPARATUS AND METHOD - A glass molding system and a method of making glass articles using the glass molding system are disclosed. The glass molding system includes an indexing table, a plurality of enclosures arranged along the indexing table, and a plurality of stations defined on the indexing table such that each of the stations is selectively indexable with any one of the enclosures. At least one radiant heater is arranged in at least one of the enclosures. A radiation reflector surface and a radiation emitter body are arranged in the at least one of the enclosures. The radiation emitter body is between the at least one radiant heater and the radiation reflector surface and has a first surface in opposing relation to the at least one radiant heater and a second surface in opposing relation to the radiation reflector surface. | 11-29-2012 |
20130098110 | GLASS MOLDING SYSTEM AND RELATED APPARATUS AND METHOD - A glass molding system and a method of making glass articles using the glass molding system are disclosed. The glass molding system includes an indexing table, a plurality of enclosures arranged along the indexing table, and a plurality of stations defined on the indexing table such that each of the stations is selectively indexable with any one of the enclosures. At least one radiant heater is arranged in at least one of the enclosures. A radiation reflector surface and a radiation emitter body are arranged in the at least one of the enclosures. The radiation emitter body is between the at least one radiant heater and the radiation reflector surface and has a first surface in opposing relation to the at least one radiant heater and a second surface in opposing relation to the radiation reflector surface. | 04-25-2013 |
20140299300 | GLASS MOLDING SYSTEM AND RELATED APPARATUS AND METHOD - A glass molding system and a method of making glass articles using the glass molding system are disclosed. The glass molding system includes an indexing table, a plurality of enclosures arranged along the indexing table, and a plurality of stations defined on the indexing table such that each of the stations is selectively indexable with any one of the enclosures. At least one radiant heater is arranged in at least one of the enclosures. A radiation reflector surface and a radiation emitter body are arranged in the at least one of the enclosures. The radiation emitter body is between the at least one radiant heater and the radiation reflector surface and has a first surface in opposing relation to the at least one radiant heater and a second surface in opposing relation to the radiation reflector surface. | 10-09-2014 |
20150321948 | METHOD AND SYSTEM FOR COATING GLASS EDGES - A process and system for applying coating materials to glass edges of various profiles. The glass edge is coated by picking up the coating material from an applicator such as, for example, a roller, through precise independent or relative control of the spatial relationship between the edge of the glass article and the applicator to achieve desirable product attributes such as coating thickness, profile, coverage areas and consistency. Such spatial relationships include the gap distance between the roller and applicator, coating thickness on the applicator, applicator and/or glass speed, and the like. | 11-12-2015 |
Patent application number | Description | Published |
20110006135 | FLUID EJECTOR HOUSING INSERT - A fluid ejector includes a fluid ejection assembly, a housing, and an insert. The fluid ejection assembly includes one or more silicon bodies and a plurality of actuators. The one or more silicon bodies includes a silicon body having a plurality of fluid passages for fluid flow and a plurality of nozzles fluidically connected to the plurality of fluid passages. The plurality of actuators cause fluid in the plurality of fluid passages to be ejected from the plurality of nozzles. The housing assembly includes one or more plastic bodies, at least one plastic body attached to at least one silicon body to form a sealed volume on a side of the fluid ejection assembly opposite the nozzles. The insert is embedded in the at least one plastic body in proximity to the at least one silicon body, the insert having a coefficient of thermal expansion of less than 9 ppm/° C. | 01-13-2011 |
20110109697 | Bonded Housing and Fluid Ejector - A method of forming a fluid ejector includes positioning a fluid ejection module such that it is adjacent to a mounting frame, applying heat to a thermohardening glue that is between the fluid ejection module and the mounting frame, and curing the glue to secure the fluid ejection module to the mounting frame. The heat is applied with a heating element at least partially embedded in the glue. | 05-12-2011 |
20110168317 | Controlled Bond Wave Over Patterned Wafer - A method of bonding two substrates includes placing a separating member between a first substrate and a second substrate, applying pressure to the first substrate to initiate a bond wave between the first substrate and the second substrates with the separating member between the first substrate and the second substrate, and controlling movement of the bond wave by translating the separating member away from a center of the first substrate or the second substrate. | 07-14-2011 |
20110209984 | Physical Vapor Deposition With Multi-Point Clamp - A physical vapor deposition apparatus includes a vacuum chamber having side walls, a cathode inside the vacuum chamber, wherein the cathode is configured to include a sputtering target, a radio frequency power supply configured to apply power to the cathode, an anode inside and electrically connected to the side walls of the vacuum chamber, a chuck inside and electrically isolated from the side walls of the vacuum chamber, the chuck configured to support a substrate, a clamp configured to hold the substrate to the chuck, wherein the clamp is electrically conductive, and a plurality of conductive electrodes attached to the clamp, each electrode configured to compress when contacted by the substrate. | 09-01-2011 |
20130292529 | Fluid Ejection Module Mounting - A bracket includes a support strut configured to carry the fluid ejection module and an alignment strut coupled to the support strut. The alignment strut is configured to affix to the frame so as to orient the support strut with respect to the frame in each of three orthogonal linear directions and three orthogonal angular directions. The alignment strut includes three alignment mechanisms. Each of the first and second alignment features is held mechanically fixed on the alignment strut in a respective aligned position, and the third alignment mechanism is movable on the alignment strut. | 11-07-2013 |
Patent application number | Description | Published |
20090208548 | COPOLYMER-STABILIZED EMULSIONS - An emulsion includes a substantially continuous liquid medium, and a plurality of droplet structures dispersed within the substantially continuous liquid medium. Each droplet structure of the plurality of droplet structures includes an outer droplet of a first liquid having an outer surface; an inner droplet of a second liquid having an inner surface contained within the outer surface of the outer droplet of the first liquid, the second liquid being immiscible in the first liquid, wherein the inner and outer droplets have a boundary surface region therebetween; an outer layer of block copolymers disposed on the outer surface of the outer droplet; and an inner layer of block copolymers disposed on the inner surface of the inner droplet. The block copolymers include a hydrophilic polymer block and a hydrophobic polymer block that act in combination to stabilize the droplet structure, and the first liquid is immiscible in the substantially continuous liquid medium. | 08-20-2009 |
20100003336 | VESICLES OF SELF-ASSEMBLING BLOCK COPOLYMERS AND METHODS FOR MAKING AND USING THE SAME - Vesicles of self-assembling block copolymers, e.g., diblock copolypeptides, as well as methods of making and using the same. Vesicles of the invention have a shell made up of block copolymers that include an intracellular transduction hydrophilic domain and a hydrophobic domain. In certain embodiments, the vesicles include an encapsulated active agent, e.g., a diagnostic or therapeutic agent. The vesicles find use in a variety of different application, including the intracellular delivery of active agents, e.g., diagnostic and therapeutic agents. | 01-07-2010 |
20130064759 | COPOLYMER-STABILIZED EMULSIONS - An emulsion includes a substantially continuous liquid medium, and a plurality of droplet structures dispersed within the substantially continuous liquid medium. Each droplet structure of the plurality of droplet structures includes an outer droplet of a first liquid having an outer surface; an inner droplet of a second liquid within the first droplet, the second liquid being immiscible in the first liquid, wherein the inner and outer droplets have a boundary surface region therebetween; an outer layer of block copolymers disposed on the outer surface of the outer droplet; and an inner layer of block copolymers disposed on the boundary surface region between the outer and the inner droplets. | 03-14-2013 |
20130267458 | COMPOSITIONS AND USES OF MATERIALS WITH HIGH ANTIMICROBIAL ACTIVITY AND LOW TOXICITY - Improved synthetic copolypeptide antimicrobials contain cationic amino acid residues and may be based on a blocky sequence. These antimicrobials show low mammalian toxicity and may undergo directed self-assembly. The inventive synthetic copolypeptides are useful in treatment of wounds and other infections. | 10-10-2013 |
20140286865 | SYNTHETIC DIBLOCK COPOLYPEPTIDE HYDROGELS FOR USE IN THE CENTRAL NERVOUS SYSTEM - This invention relates, e.g., to a composition suitable for administration to the central nervous system (CNS), comprising a block copolypeptide hydrogel, which comprises a biologically active material that is mixed with the hydrogel or that is attached to the polypeptide chain of the hydrogel, wherein the composition is suitable for administration to the CNS. Also disclosed are methods of making and using compositions of the invention as depots or as scaffolds for cell migration, and pharmaceutical compositions and kits for implementing methods of the invention. | 09-25-2014 |
20150057433 | PREPARATION OF FUNCTIONALIZED POLYPEPTIDES, PEPTIDES, AND PROTEINS BY ALKYLATION OF THIOETHER GROUPS - Reagents are disclosed for chemoselective tagging of methionine residues in peptides and polypeptides, subsequent bioorthogonal tag functionalization, and cleavage of the tags when desired to regenerate unmodified samples. This method compliments other peptide tagging strategies and adds capability for tag removal, which may be useful for release of therapeutic peptides from a carrier, or release of tagged protein digests from solid supports. | 02-26-2015 |
20150366193 | COMPOSITION WITH HIGH ANTIMICROBIAL ACTIVITY AND LOW TOXICITY - Improved synthetic copolypeptide antimicrobials contain cationic amino acid residues and may be based on a blocky sequence. These antimicrobials show low mammalian toxicity and may undergo directed self-assembly. The inventive synthetic copolypeptides are useful in treatment of wounds and other infections. | 12-24-2015 |
20160002405 | AMPHIPHILIC DERIVATIVES OF THIOETHER CONTAINING BLOCK COPOLYPEPTIDES - Methods for preparation of novel amphiphilic derivatives of thioether containing block copolypeptides with narrow chain length distributions are described. These block copolymers can be chemically modified by oxidation and alkylation of the thioether containing residues. These materials generate self-assembled micelles, vesicles and hydrogels, or emulsions with oil phases. These assemblies can be used to encapsulate and delivery therapeutic molecules. The assemblies can be taken up by cells to release molecules from the assemblies. | 01-07-2016 |