Degroote
Laurent Degroote, Caestre FR
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20090220712 | Polyester composition comprising silica particles and use thereof for making packaging articles - The polymeric composition comprising (A) a polyester resin and (B) micrometrical silica particles, preferably particles made of cristobalite or quartz, dispersed in the polyester resin preferably at concentration of at least 2 wt %. The polyester resin preferably comprises a PET homo or copolymer. Packaging articles, especially biaxially stretched blow moulded containers, made with the said polymeric composition exhibit high opacity to UV and visible light radiations as well as improved barrier properties to O | 09-03-2009 |
Stefan Degroote, Scherpenheuvel-Zichem BE
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20110005455 | Method for Manufacturing a Mono-Crystalline Layer on a Substrate - The present invention is related to a method for growing a layer of a mono-crystalline material on a substrate comprising | 01-13-2011 |
20110101370 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions. | 05-05-2011 |
20110108850 | METHOD OF MANUFACTURING AN INTEGRATED SEMICONDUCTOR SUBSTRATE STRUCTURE - An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed. | 05-12-2011 |
20130203221 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions. | 08-08-2013 |
Stefan Degroote, Scherpenheuven-Zichem BE
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20090294777 | METHOD FOR FORMING A GROUP III NITRIDE MATERIAL ON A SILICON SUBSTRATE - Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 μmol/cm | 12-03-2009 |
20100173127 | METHOD FOR PRODUCING A CRYSTALLINE GERMANIUM LAYER ON A SUBSTRATE - The present invention provides a method for providing a crystalline germanium layer on a crystalline base substrate having a crystalline surface. The method comprises cleaning the base substrate for removing contaminants and/or native oxides from the surface, providing an amorphous germanium layer on the surface of the base substrate while exposing to the base substrate to a hydrogen source such as e.g. a hydrogen plasma, a H | 07-08-2010 |
20110089520 | GROWTH OF MONOCRYSTALLINE GeN ON A SUBSTRATE - The present invention relates a method for forming a monocrystalline GeN layer ( | 04-21-2011 |
Stefan Degroote, Scherpenheuvel BE
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20090189192 | DEPOSITION OF GROUP III-NITRIDES ON Ge - The present invention provides a method for depositing or growing a group III-nitride layer, e.g. GaN layer ( | 07-30-2009 |
Stefan Degroote, Scherpenheuval-Zichem BE
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20140159119 | Method for Growing III-V Epitaxial Layers and Semiconductor Structure - Disclosed are methods of growing III-V epitaxial layers on a substrate, a semiconductor structure comprising a substrate, a device comprising such a semiconductor structure, and an electronic circuit. Group III-nitride devices, such as, for example, high-electron-mobility transistors, may include a two-dimensional electron gas (2DEG) between two active layers. For example, the 2DEG may be between a GaN layer and a AlGaN layer. These transistors may work in depletion-mode operation, which means the channel has to be depleted to turn the transistor off. For certain applications, such as, for example, power switching or integrated logic, negative polarity gate supply is undesired. Transistors may then work in enhancement mode (E-mode). | 06-12-2014 |
20140167114 | Method for Growing III-V Epitaxial Layers - Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device. | 06-19-2014 |