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Deepak Ramappa

Deepak Ramappa, Boston, MA US

Patent application numberDescriptionPublished
20110104618SELF-ALIGNED MASKING FOR SOLAR CELL MANUFACTURE - Various methods of utilizing the physical and chemical property differences between amorphized and crystalline silicon are used to create masks that can be used for subsequent implants. In some embodiments, the difference in film growth between amorphous and crystalline silicon is used to create the mask. In other embodiments, the difference in reflectivity or light absorption between amorphous and crystalline silicon is used to create the mask. In other embodiments, differences in the characteristics of doped and undoped silicon is used to create masks.05-05-2011

Deepak Ramappa, Cambridge, MA US

Patent application numberDescriptionPublished
20100041246Cleaving Of Substrates - An improved process of substrate cleaving and a device to perform the cleaving are disclosed. In the traditional cleaving process, a layer of microbubbles is created within a substrate through the implantation of ions of a gaseous species, such as hydrogen or helium. The size and spatial distribution of these microbubbles is enhanced through the use of ultrasound energy. The ultrasound energy causes smaller microbubbles to join together and also reduces the straggle. An ultrasonic transducer is acoustically linked with the substrate to facilitate these effects. In some embodiments, the ultrasonic transducer is in communication with the platen, such that ultrasound energy can be applied during ion implantation and/or immediately thereafter. In other embodiments, the ultrasonic energy is applied to the substrate during a subsequent process, such as an anneal.02-18-2010
20100110239DARK CURRENTS AND REDUCING DEFECTS IN IMAGE SENSORS AND PHOTOVOLTAIC JUNCTIONS - Dark currents within a photosensitive device are reduced through improved implantation of a species during its fabrication. Dark currents can be caused by defects in the photo-diode device, caused during the annealing, implanting or other processing steps used during fabrication. By amorphizing the workpiece in the photo-diode region, the number of defects can be reduced thereby reducing this cause of dark current. Dark current is also caused by stress induced by an adjacent STI, where the stress caused by the liner and fill material exacerbate defects in the workpiece. By amorphizing the sidewalls and bottom surface of the trench, defects created during the etching process can be reduced. This reduction in defects also decreases dark current in the photosensitive device.05-06-2010
20100112788METHOD TO REDUCE SURFACE DAMAGE AND DEFECTS - A method of implantation that minimizes surface damage to a workpiece is disclosed. In one embodiment, following a doping implant, a second implant is performed which causes the silicon at the surface of the workpiece to become amorphous. This reduces surface damage and interstitials, which has several benefits. First, inactive dopant clusters may become activated due to the replenishment of silicon. Secondly, the amorphous nature of the silicon makes it bond more easily in subsequent process steps, such as silicidation.05-06-2010
20100155909METHOD TO ENHANCE CHARGE TRAPPING - Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.06-24-2010

Deepak Ramappa, Dallas, TX US

Patent application numberDescriptionPublished
20090102501TEST STRUCTURES FOR E-BEAM TESTING OF SYSTEMATIC AND RANDOM DEFECTS IN INTEGRATED CIRCUITS - In accordance with the invention, there are electron beam inspection systems, electron beam testable semiconductor test structures, and methods for detecting systematic defects, such as, for example contact-to-gate shorts, worm hole leakage paths, holes printing issues, and anomalies in sparse holes and random defects, such as, current leakage paths due to dislocations and pipes during semiconductor processing.04-23-2009