Patent application number | Description | Published |
20090121353 | DUAL DAMASCENE BEOL INTEGRATION WITHOUT DUMMY FILL STRUCTURES TO REDUCE PARASITIC CAPACITANCE - In accordance with the invention, there are methods of making semiconductor devices. The method can include forming a hard mask layer over a dielectric layer, forming a via through the hard mask layer and the dielectric layer, and depositing an anti-reflective coating in the via and over the hard mask layer. The method can also include etching a trench through the hard mask layer, etching a dummy fill pattern in the hard mask layer to a desired thickness, and etching the trench through the dielectric layer and the dummy fill through the hard mask layer and in the dielectric layer. The method can further include depositing copper in the via and in the trench and removing excess copper using chemical mechanical polishing, wherein the dummy fill in the dielectric layer is of desired reduced depth. | 05-14-2009 |
20100084580 | THERMAL MODULATION OF IMPLANT PROCESS - A method for ion implantation is disclosed which includes modulating the temperature of the substrate during the implant process. This modulation affects the properties of the substrate, and can be used to minimize EOR defects, selectively segregate and diffuse out secondary dopants, maximize or minimize the amorphous region, and vary other semiconductor parameters. In one particular embodiment, a combination of temperature modulated ion implants are used. Ion implantation at higher temperatures is used in sequence with regular baseline processing and with ion implantation at cold temperatures. The temperature modulation could be at the beginning or at the end of the process to alleviate the detrimental secondary dopant effects. | 04-08-2010 |
20100279479 | Formation Of Raised Source/Drain On A Strained Thin Film Implanted With Cold And/Or Molecular Carbon - A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing one or more cold-carbon or molecular carbon ion implantation steps to implant carbon ions within the semiconductor structure to create strain layers on either side of a channel region. Raised source/drain regions are then formed above the strain layers, and subsequent ion implantation steps are used to dope the raised source/drain region. A millisecond anneal step activates the strain layers and the raised source/drain regions. The strain layers enhances carrier mobility within a channel region of the semiconductor structure, while the raised source/drain regions minimize reduction in strain in the strain layer caused by subsequent implantation of dopant ions in the raised source/drain regions. | 11-04-2010 |
20100323113 | Method to Synthesize Graphene - A method of using ion implantation techniques to create graphene is disclosed. Carbon ions are implanted in a substrate, such as a metal foil, using a plasma doping system or a beam line implanter. The implant is performed at an elevated temperature, to allow a large number of carbon ions to be absorbed by the foil. As the temperature is reduced, the excessive number of carbon atoms causes the foil to be saturated, and the carbon atoms diffuse to the surface, thereby producing graphene. In another embodiment, a plasma doping system is used, where a plasma containing carbon and other species is created. These additional species are also implanted, thereby causing the diffused atoms to contain both carbon and the additional species. | 12-23-2010 |
20110097840 | REDUCING SURFACE RECOMBINATION AND ENHANCING LIGHT TRAPPING IN SOLAR CELLS - Methods of improving the anti-reflection properties of one or more dielectric layers and reducing surface recombination of generated carriers of a solar cell are disclosed. In some embodiments, dopants are introduced into the dielectric layers to improve their anti-reflection properties. In other embodiments, species are introduced into the dielectric layers to create electrical fields which repel the minority carriers away from the surface and toward the contacts. In another embodiment, mobiles species are introduced to the anti-reflective coating, which cause carrier to be repelled from the surface of the solar cell. By creating a barrier at the surface of the solar cell, undesired recombination at the surface may be reduced. | 04-28-2011 |
20110124186 | APPARATUS AND METHOD FOR CONTROLLABLY IMPLANTING WORKPIECES - A plasma processing apparatus comprises a plasma source configured to produce a plasma in a plasma chamber, such that the plasma contains ions for implantation into a workpiece. The apparatus also includes a focusing plate arrangement having an aperture arrangement configured to modify a shape of a plasma sheath of the plasma proximate the focusing plate such that ions exiting an aperture of the aperture arrangement define focused ions. The apparatus further includes a processing chamber containing a workpiece spaced from the focusing plate such that a stationary implant region of the focused ions at the workpiece is substantially narrower that the aperture. The apparatus is configured to create a plurality of patterned areas in the workpiece by scanning the workpiece during ion implantation. | 05-26-2011 |
20110127885 | CLEAVING OF SUBSTRATES - An improved process of substrate cleaving and a device to perform the cleaving are disclosed. In the traditional cleaving process, a layer of microbubbles is created within a substrate through the implantation of ions of a gaseous species, such as hydrogen or helium. The size and spatial distribution of these microbubbles is enhanced through the use of ultrasound energy. The ultrasound energy causes smaller microbubbles to join together and also reduces the straggle. An ultrasonic transducer is acoustically linked with the substrate to facilitate these effects. In some embodiments, the ultrasonic transducer is in communication with the platen, such that ultrasound energy can be applied during ion implantation and/or immediately thereafter. In other embodiments, the ultrasonic energy is applied to the substrate during a subsequent process, such as an anneal. | 06-02-2011 |
20110151610 | WORKPIECE PATTERNING WITH PLASMA SHEATH MODULATION - Methods to texture or fabricate workpieces are disclosed. The workpiece may be, for example, a solar cell. This texturing may involve etching or localized sputtering using a plasma where a shape of a boundary between the plasma and the plasma sheath is modified with an insulating modifier. The workpiece may be rotated in between etching or sputtering steps to form pyramids. Regions of the workpiece also may be etched or sputtered with ions formed from a plasma adjusted by an insulating modifier and doped. A metal layer may be formed on these doped regions. | 06-23-2011 |
20110204264 | ION IMPLANTATION THROUGH LASER FIELDS - Ions are generated and directed toward a workpiece. A laser source generates a laser that is projected above the workpiece in a line. As the laser is generated, a fraction of the ions are blocked by the laser. This may enable selective implantation or modification of the workpiece. In one particular embodiment, the lasers are generated while ions are directed toward the workpiece and then stopped. Ions are still directed toward the workpiece after the lasers are stopped. | 08-25-2011 |
20110259408 | METHOD FOR PATTERNING A SUBSTRATE USING ION ASSISTED SELECTIVE DEPOSITION - A method of patterning a substrate includes providing a focusing plate adjacent to a plasma chamber containing a plasma, the focusing plate configured to extract ions from the plasma through at least one aperture that provides focused ions towards the substrate. The method further includes directing first ions through the at least one aperture to one or more first regions of the substrate so as to condense first gaseous species provided in ambient of the substrate on the one or more first regions of the substrate. | 10-27-2011 |
20140038393 | METHOD AND SYSTEM FOR ION-ASSISTED PROCESSING - A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate. | 02-06-2014 |
Patent application number | Description | Published |
20080299718 | DAMASCENE PROCESS HAVING RETAINED CAPPING LAYER THROUGH METALLIZATION FOR PROTECTING LOW-K DIELECTRICS - A method of forming single or dual damascene interconnect structures using either a via-first or trench first approach includes the steps of providing a substrate surface having an etch-stop layer thereon, a low-k dielectric layer on the etch-stop layer, and a dielectric capping layer on the low-k dielectric layer. In the single damascene process using trench pattern, a trench is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the via-first process, using a via pattern, the via is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the trench first process, using the via pattern the via is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the single damascene or either via-first or trench-first dual damascene embodiment, the capping layer is retained over the low-k dielectric layer on top surfaces of the trench into the metal processing, generally including CMP processing, wherein the CMP process removes at least a portion, and in one embodiment the entire, capping layer. | 12-04-2008 |
20090017564 | METHOD TO DETECT AND PREDICT METAL SILICIDE DEFECTS IN A MICROELECTRONIC DEVICE DURING THE MANUFACTURE OF AN INTEGRATED CIRCUIT - The present invention provides a method detecting metal silicide defects in a microelectronic device. The method comprises positioning ( | 01-15-2009 |
20090087938 | Method for Manufacturing Microdevices or Integrated Circuits on Continuous Sheets - Current manufacturing of miniature or micro electronic mechanical optical chemical or biophysical devices utilizes discrete substrates holding one or more said devices. The use of discrete substrates entails several disadvantages with respect to economical manufacturing. This invention is a method of manufacturing devices using flexible carrier sheets with device substrates attached to the carrier sheet, storage/transport devices for the carrier sheet, and process tools capable of continuous processing of the carrier sheets. | 04-02-2009 |
20090170221 | Etch residue reduction by ash methodology - Methods for forming dual damascene interconnect structures are provided. The methods incorporate an ashing operation comprising a first ash operation and a second overash operation. The ashing operation is performed prior to etching of an etch stop layer. The operation removes residue from a cavity formed during formation of the interconnect structure and facilitates better CD control without altering the cavity profiles. | 07-02-2009 |
20090212793 | STRUCTURES FOR TESTING AND LOCATING DEFECTS IN INTEGRATED CIRCUITS - A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices. | 08-27-2009 |
20100136781 | SIMULTANEOUS VIA AND TRENCH PATTERNING USING DIFFERENT ETCH RATES - One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal. | 06-03-2010 |
Patent application number | Description | Published |
20130064989 | PLASMA PROCESSING OF WORKPIECES TO FORM A COATING - A surface of an insulating workpiece is implanted to form either hydrophobic or hydrophilic implanted regions. A conductive coating is deposited on the workpiece. The coating may be a polymer in one instance. This coating preferentially forms either on the implanted regions if these implanted regions are hydrophilic or on the non-implanted regions if the implanted regions are hydrophobic. | 03-14-2013 |
20130234034 | APPARATUS AND METHOD FOR CONTROLLABLY IMPLANTING WORKPIECES - A plasma processing apparatus comprises a plasma source configured to produce a plasma in a plasma chamber, such that the plasma contains ions for implantation into a workpiece. The apparatus also includes a focusing plate arrangement having an aperture arrangement configured to modify a shape of a plasma sheath of the plasma proximate the focusing plate such that ions exiting an aperture of the aperture arrangement define focused ions. The apparatus further includes a processing chamber containing a workpiece spaced from the focusing plate such that a stationary implant region of the focused ions at the workpiece is substantially narrower that the aperture. The apparatus is configured to create a plurality of patterned areas in the workpiece by scanning the workpiece during ion implantation. | 09-12-2013 |
20140120647 | TECHNIQUES FOR MANUFACTURING DEVICES - Techniques for manufacturing a device are disclosed. In accordance with one exemplary embodiment, the technique may be realized as a method for forming a solar cell. The method may comprise: implanting p-type dopants into a substrate via a blanket ion implantation process; implanting n-type dopants into the substrate via the blanket ion implantation process; and performing a first annealing process to form the p-type region and performing a second annealing process to form a second n-type region. | 05-01-2014 |
20140202633 | METHOD AND SYSTEM FOR ION-ASSISTED PROCESSING - A system for processing a substrate includes a plasma chamber to produce a plasma including reactive gas ions at a first pressure, a bias supply to supply a bias between the plasma chamber and the substrate, a plasma sheath modifier disposed between the plasma chamber and substrate, the plasma sheath modifier having an aperture configured to direct the reactive ions toward the substrate in a beam having an ion beam profile, and a process chamber enclosing the substrate, the process chamber at a second pressure different than the first pressure to define a pressure differential. | 07-24-2014 |
20140273330 | METHOD OF FORMING SINGLE SIDE TEXTURED SEMICONDUCTOR WORKPIECES - Methods of creating a workpiece having a smooth side and a textured side are disclosed. In some embodiments, a first side of a workpiece is doped, using ion implantation or diffusion, to create a doped layer. This doped layer of the first side may be more resistant to chemical treatment than the second side of the workpiece. This allows the second side of the workpiece to be textured without capping or otherwise protecting the doped first side, even though the doped layer of the first side physically contacts the chemical treatment. In some embodiments, a p-type dopant is used to create the doped layer. In some embodiments, the workpiece is processed to form a solar cell. | 09-18-2014 |