| Patent application number | Description | Published |
|---|
| 20090027126 | METHOD FOR ADAPTIVE BIASING OF FULLY DIFFERENTIAL GAIN BOOSTED OPERATIONAL AMPLIFIERS - An adaptive biasing technique improves fully differential gain boosted operational amplifiers transient characteristics and reduces power consumption. An adaptive biasing module includes a bias generation module and a bias replication module. The bias generation module generates a first control signal (VCMNB) and the first control signal is applied as an output common mode of a differential booster (inside the bias replication module). The bias replication module is coupled to the bias generation module for equalizing a common mode of the differential booster with the first control signal (VCMNB). | 01-29-2009 |
| 20100117710 | SWITCHED CHARGE STORAGE ELEMENT NETWORK - A switched charge storage element integrator in a continuous or discrete time circuit, the integrator including a differential input amplifier, a first 2-terminal charge storage element, a second 2-terminal charge storage element, and a plurality of controlled switches. The differential input amplifier is coupled to a capacitor and a resistor and configured as an inverting integrator. An inverting terminal of the amplifier is coupled to two controlled switches. A non-inverting terminal of the amplifier is coupled to a reference voltage. The first and second switched charge storage element blocks are alternatingly coupled to the inverting terminal INM of the amplifier XOPA during the active state of a second clock signal and a first clock signal, respectively, for making the supply noise continuous and eliminating its dependency on the clock phases, thereby zeroing its convolution with the clock signal. | 05-13-2010 |
| 20110001518 | OPERATING A SWITCHED-CAPACITOR CIRCUIT WITH REDUCED NOISE - Techniques for operating a switched-capacitor circuit to reduce input and feedback dependence and/or reduce reference modulation. A switched-capacitor circuit can be operated in four phases. In a first phase at a start of a cycle, the capacitor is charged/discharged by a common mode signal to mask any residual charge stored in the capacitor from a previous cycle. In a second phase, the capacitor is charged with an input signal. During a third phase, the capacitor is charged with a wide-bandwidth auxiliary reference signal, and during a fourth phase the capacitor is charged with a reference signal. During the third and fourth phases, the capacitor may be coupled to an integrating to circuit to integrate a difference between the input signal and the reference signal. | 01-06-2011 |
| 20110032136 | REDUCTION IN KICKBACK EFFECT IN COMPARATORS - The present disclosure relates to reduction in the effect of kickback in comparators by means of charge injection implemented by means of voltage controlled switches with attributes similar to those of an input differential pair. The voltage controlled switches produce charge to neutralize the charge loss during latching of inputs in the comparator. | 02-10-2011 |
