Patent application number | Description | Published |
20090313592 | METHOD TO DESIGN NETWORK-ON-CHIP (NOC) - BASED COMMUNICATION SYSTEMS - A method to design a Networks on Chips (NoCs)-based communication system for connecting on-chip components in a multicore system, said system comprising several elements communicating through the communication system, said communication system comprising at least switches, said method comprising the steps of modelling the applications running on the multicore system, establishing the number and configuration of switches to connect the elements, establishing physical connectivity between the elements and the switches, for each two pairs of communicating elements: (a) a defining a communication path, (b) calculating metrics as affected by the need to render said path into physical connectivity, taking into account any previously defined physical connectivity, (c) iterating the steps a and b for a plurality of possible paths, (d) choosing the path having the optimal metrics, and (e) establishing any missing physical connectivity between the switches so that the selected optimal path occurs across physically connected switches. | 12-17-2009 |
20100080124 | METHOD TO MANAGE THE LOAD OF PERIPHERAL ELEMENTS WITHIN A MULTICORE SYSTEM - A method to provide reliability, power management and load balancing support for multicore systems based on Networks-on-Chip (NoCs) and to efficiently implement architectural support for this method by introducing complex packet handling mechanisms is achieved by modifying the basic network interfaces attached to the cores of multicore computation systems. It also proposes policies to leverage the proposed hardware extensions. This aim is achieved with a method to manage the load of peripheral elements within a multicore system comprising several processing units accessing peripheral elements through a NoC, each processing unit and peripheral element attached to a Network Interface in charge of formatting and driving the packets sent to or received from the NoC, wherein, while considering at least two peripheral elements having a similar function, the Network Interface dedicated to a first peripheral element reroutes the incoming packets to a second Network Interface dedicated to a second peripheral element. | 04-01-2010 |
20130313524 | AMBIPOLAR SILICON NANOWIRE FIELD EFFECT TRANSISTOR - This invention describes a novel electronic device consisting of one—or more—vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central section of the transistor channel, controls on/off behavior of the channel. The second gate, acting on the regions in proximity to the source and the drain of the transistor, defines the polarity of the devices, i.e. p or n type. The electric field of the second gate acts either at the interface of the nanowire-to-source/drain region or anywhere in close proximity to the depleted region of the SiNW body, modulating the bending of the Schottky barriers at the contacts, eventually screening one type of charge carrier to pass through the channel of the transistor. This is achieved by controlling the majority carriers passing through the transistor channel by regulating the Schottky barrier thicknesses at the source and drain contacts. | 11-28-2013 |
20140043060 | CONTROLLABLE POLARITY FET BASED ARITHMETIC AND DIFFERENTIAL LOGIC - A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output. | 02-13-2014 |