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De Jong, CA
Bastiaan De Jong, Rancho Santa Margarita, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090159271 | Top drive systems for wellbore & drilling operations - A top drive system for wellbore operations, the top drive system in certain aspects including a main body, a motor (in certain aspects a salient pole motor), a motor apparatus, a motor shaft extending from the motor, a gear system driven by the motor shaft and interconnected with a drive shaft, the gear system driven by the motor apparatus so that driving the gear system drives the drive shaft, the gear system having a housing and a bearing retainer integral with the housing. This abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims, 37 C.F.R. 1.72(b). | 06-25-2009 |
| 20110100622 | Top Drive Systems for Wellbore & Drilling Operations - A top drive system for wellbore operations and method for facilitating rotation thereof. The system includes a main body and a motor, preferably a salient pole motor. A motor shaft extends from the motor and a gear system is driven by the shaft and interconnected with a drive shaft. The gear system has a housing and a bearing retainer integral with the housing and is driven by the motor apparatus so that driving the gear system drives the drive shaft. | 05-05-2011 |
Chad De Jong, Los Angeles, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090154722 | Audio Receiving Device And Method Of Forming Same - In some embodiments, an audio receiving device can be configured to couple to and produce an output signal for a portable media device. The audio receiving system can include: (a) a first microphone; (b) a second microphone; (c) a housing; and (d) an audio interface configured to electrically couple to the portable media device and provide the output signal to the portable media device. The first microphone can be coupled to the housing such that the first microphone can be rotated relative to the housing. Similarly, the second microphone can be coupled to the housing such that the second microphone can be rotated relative to the housing. Other embodiments are disclosed in this application. | 06-18-2009 |
Duane De Jong, Elk Grove, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090195514 | CONTROLLER USER INTERFACE FOR A CATHETER LAB INTRAVASCULAR ULTRASOUND SYSTEM - A touchpad controller for a componentized intravascular ultrasound system is disclosed for acquisition and display of intravascular information in a catheter lab environment. The system includes a patient interface module (PIM) adapted to hold a catheter having an imaging probe located near a distal end, a control panel, a monitor for displaying images and patient data, and a processing unit. The touchpad controller facilitates use beneath a sterile drape and sensitivity to gloved touch. Furthermore, the touchpad controller is sized for handheld use during an imaging session. A rail mount facilitates easy attachment of the touchpad controller alongside a patient table. | 08-06-2009 |
Jan L. De Jong, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110210443 | SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATION AND METHOD OF FORMING SAME - An embodiment of a method of forming a semiconductor device that includes a substrate having an active layer and interconnect formed on the active layer is described. The method includes: forming a dielectric layer above the interconnect having a tapered via exposing at least a portion of a first metal layer; forming an under-bump metallization (UBM) layer over the tapered via and the first metal layer to form a UBM bucket; and forming a dielectric cap layer over the dielectric layer and a portion of the UBM layer. The UBM bucket is configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated. | 09-01-2011 |
Jan Lodewijk De Jong, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100127309 | INTEGRATED CAPACITOR WITH ALTERNATING LAYERED SEGMENTS - A capacitor in an integrated circuit (“IC”) has a first node plate link formed in a first metal layer of the IC electrically connected to and forming a portion of a first node of the capacitor extending along a first axis (y) and a second node plate link formed in a second metal layer of the IC extending along the axis and connected to the first node plate with a via. A third node plate link formed in the first metal layer is electrically connected to and forming a portion of a second node of the capacitor and extends along a second axis (x) of the node plate array transverse to the first node plate link, proximate to an end of the first node plate link and overlying a portion of the second node plate link. | 05-27-2010 |
J.l. De Jong, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110084314 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern. | 04-14-2011 |
| 20110121366 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device includes a first single crystal silicon layer including first transistors, a first alignment mark, and at least one metal layer overlying the first single crystal silicon layer for interconnecting the first transistors; a second layer overlying the at least one metal layer, wherein the second layer includes a plurality of second transistors; and a connection path connecting the first transistors and the second transistors and including at least a first strip, a second strip, and a through via connecting the first strip and the second strip, wherein the second strip is substantially orthogonal to the first strip and wherein the through via is substantially away from both ends of the first strip and both ends of the second strip. | 05-26-2011 |
J. L. De Jong, Cupertino, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100289064 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layers; wherein the second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands wherein each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern. | 11-18-2010 |
| 20100291749 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks. | 11-18-2010 |
| 20100295136 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors. | 11-25-2010 |
| 20110049577 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern. | 03-03-2011 |
| 20110092030 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells. | 04-21-2011 |
| 20110108888 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells. | 05-12-2011 |
| 20110199116 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A Configurable device comprising, a logic die connected by at least one through silicon-via (TSV), to an input/output (I/O) die. | 08-18-2011 |
Rinaldo Laurentius De Jong, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100331357 | PHARMACEUTICAL COMPOSITION - The present invention provides a pharmaceutical composition, wherein solubility and stability of a water-insoluble or slightly water-soluble compound represented by formula (I): wherein each symbol is as defined in the specification, are improved, by combination of the above-mentioned compound and a cyclodextrin derivative and a method for improving solubility, stability and the like of the above-mentioned compound. | 12-30-2010 |