| Patent application number | Description | Published |
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| 20100293401 | Power Managed Lock Optimization - In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free. | 11-18-2010 |
| 20110252251 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 10-13-2011 |
| 20120144172 | Interrupt Distribution Scheme - In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor. | 06-07-2012 |
| 20120167107 | Power Managed Lock Optimization - In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free. | 06-28-2012 |
| 20120185703 | Coordinating Performance Parameters in Multiple Circuits - Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles. | 07-19-2012 |
| 20120260081 | Adjusting Device Performance Based on Processing Profiles - Adjusting processor performance based on processing profiles. The method may determine that a process has entered a processing state after an idle state. In response to entering the processing state the processing time of the processor may be monitored. In response to the processing time exceeding a first threshold of time, the performance of the processor may be increased from a first level to a second level. In response to the processing time exceeding a second threshold time, the performance of the processor may be decreased from the second level to a third level. | 10-11-2012 |
| Patent application number | Description | Published |
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| 20080307245 | Methods and systems to dynamically manage performance states in a data processing system - Methods and apparatuses to dynamically manage a performance state of a data processing system are described. The data processing system includes a plurality of components; one or more buses coupled to the plurality of components, and a dynamic performance state manager unit coupled to the components. The dynamic performance state manager unit is configured to receive information about a first plurality of current states of components of the system. The dynamic performance state manager unit is configured to determine a second plurality of required system performance states for the components; and to determine a current system performance state based on the first plurality and the second plurality. | 12-11-2008 |
| 20090063108 | Compatible trust in a computing device - A method and apparatus for executing a first executable code image having a first version number into a memory of a device in an attempt to establish an operating environment of the device are described. The first executable code image retrieves a second version number from the second executable code image after successfully authenticating the second executable code image. If the first version number and the second version number do not satisfy a predetermined relationship, the second executable code image is prevented from being loaded by the first executable code image. | 03-05-2009 |
| 20090063715 | METHODS AND SYSTEMS TO DYNAMICALLY MANAGE PERFORMANCE STATES IN A DATA PROCESSING SYSTEM - Data processing systems which operate in different modes, including a mode which supports providing an output of images through a port on the systems. In one embodiment, a data processing system includes a processing system, a cellular telephone transceiver, and a port which is configured to provide, as an output from the handheld data processing system, data representing movie video images. Methods and machine readable media are also described. | 03-05-2009 |
| 20090257595 | Single Security Model In Booting A Computing Device - A method and apparatus for securely booting software components in an electronic device to establish an operating environment are described herein. According to an aspect of the invention, software components are to be executed in sequence in order to establish an operating environment of a device. For each software component, a security code is executed to authenticate and verify an executable code image associated with each software component using one or more keys embedded within a secure ROM (read-only memory) of the device and one or more hardware configuration settings of the device. The security code for each software component includes a common functionality to authenticate and verify the executable code image associated with each software component. In response to successfully authenticating and verifying the executable code image, the executable code image is then executed in a main memory of the device to launch the associated software component. | 10-15-2009 |
| 20090259855 | Code Image Personalization For A Computing Device - A method and apparatus for personalizing a software component to be executed in particular environment are described herein. According to an aspect of the invention, in response to an executable code image representing a software component to be installed in an electronic device, the executable code image is encrypted using an encryption key. The encryption key is then wrapped with a UID that uniquely identifies the electronic device, where the UID is embedded within a secure ROM of the electronic device. The wrapped encryption key and the encrypted executable code image are then encapsulated into a data object to be stored in a storage of the electronic device, such that when the electronic device is subsequently initialized for operation, the executable code image can only be recovered using the UID of the electronic device to retrieve a decryption key in order to decrypt the executable code image. | 10-15-2009 |
| 20090295461 | DEVICE CONFIGURATION - A process and apparatus for configuring one or more integrated circuits within a device in a manufacturing process is described. In an exemplary process, a device is manufactured by assembling a chip onto a board such as a printed circuit substrate and the chip is fused from power routed across the board to the chip. The power source for the fusing can be generated from the internal power supply on the board or received on a test point on the board itself or a connection interface (e.g. a USB interface) coupled to the board. In an exemplary apparatus, a device comprises a chip with a plurality of fuses that are used to configure the device and a board coupled to the chip, with the board capable of routing power from the board to the chip and the power is used to blow one or more of the plurality of fuses. | 12-03-2009 |
| 20100211700 | METHODS AND SYSTEMS TO DYNAMICALLY MANAGE PERFORMANCE STATES IN A DATA PROCESSING SYSTEM - Data processing systems which operate in different modes, including a mode which supports providing an output of images through a port on the systems. In one embodiment, a data processing system includes a processing system, a cellular telephone transceiver, and a port which is configured to provide, as an output from the handheld data processing system, data representing movie video images. Methods and machine readable media are also described. | 08-19-2010 |
| 20110219252 | Methods and Systems for Power Management in a Data Processing System - Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions. | 09-08-2011 |
| 20110258640 | METHOD AND APPARATUS FOR INTERCOMMUNICATIONS AMONGST DEVICE DRIVERS - Techniques for intercommunication amongst device drivers are described herein. In one embodiment, an application programming interface (API) is provided by a kernel of an operating system (OS) running within a data processing system. The API is accessible by device drivers associated with multiple devices installed in the system. In response to a request from a first instance of a driver the API, information indicating whether another instance of the same driver is currently started is returned via the API. Other methods and apparatuses are also described. | 10-20-2011 |
| 20110283023 | METHODS AND SYSTEMS TO DYNAMICALLY MANAGE PERFORMANCE STATES IN A DATA PROCESSING SYSTEM - Data processing systems which operate in different modes, including a mode which supports providing an output of images through a port on the systems. In one embodiment, a data processing system includes a processing system, a cellular telephone transceiver, and a port which is configured to provide, as an output from the handheld data processing system, data representing movie video images. Methods and machine readable media are also described. | 11-17-2011 |
| 20110314305 | Dynamic Voltage Dithering - A request for a high voltage mode is received and a high voltage timer is started in response to determining that a remaining amount of high voltage credits exceeds a voltage switch threshold value. A switch to the high voltage mode is made in response to the request. A low voltage mode is switched to in response to an indication. The request may be received from an application running on a data processing system. If the indication is that the high voltage timer has expired, a low voltage timer is started in response to switching to low voltage mode. If the high voltage request is still active when the low voltage timer expires, a switch back to high voltage mode occurs and a new high voltage timer is started. | 12-22-2011 |
| 20120166781 | SINGLE SECURITY MODEL IN BOOTING A COMPUTING DEVICE - A method and apparatus for securely booting software components in an electronic device to establish an operating environment are described herein. According to an aspect of the invention, software components are to be executed in sequence in order to establish an operating environment of a device. For each software component, a security code is executed to authenticate and verify an executable code image associated with each software component using one or more keys embedded within a secure ROM (read-only memory) of the device and one or more hardware configuration settings of the device. The security code for each software component includes a common functionality to authenticate and verify the executable code image associated with each software component. In response to successfully authenticating and verifying the executable code image, the executable code image is then executed in a main memory of the device to launch the associated software component. | 06-28-2012 |
| 20120185712 | METHODS AND SYSTEMS FOR POWER MANAGEMENT IN A DATA PROCESSING SYSTEM - Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions. | 07-19-2012 |
