| Patent application number | Description | Published |
|---|
| 20080253217 | Method for accessing a memory cell in an integrated circuit, method of determining a set of word line voltage identifiers in an integrated circuit, method for classifying memory cells in an integrated circuit, method for determining a word line voltage for accessing a memory cell in an integrated circuit and integrated circuits - Embodiments of the invention relate to a method for accessing a memory cell in an integrated circuit, a method of determining a set of word line voltage identifiers in an integrated circuit, a method for classifying memory cells in an integrated circuit, a method for determining a word line voltage for accessing a memory cell in an integrated circuit and integrated circuits. In an embodiment, a method of accessing a memory cell in an integrated circuit, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes selecting a word line voltage identifier from a pre-stored set of word line voltage identifiers, each one of the pre-stored set of word line voltage identifiers being assigned to at least one of the memory cells in the memory cell field and accessing the memory cell using a word line voltage being dependent on the selected word line voltage identifier. | 10-16-2008 |
| 20080306723 | Emulated Combination Memory Device - An integrated circuit memory device and a method of providing access to multiple memory types within a single integrated circuit memory device are described. In various embodiments, the integrated circuit memory device includes a non-volatile memory array having a first emulated memory region and a second emulated memory region, and a controller having an interface. The memory device is configured to emulate a first emulated memory type and a second emulated memory type. The memory device is further configured to store data in the first emulated memory region when the memory device emulates the first emulated memory type, and in the second emulated memory region when the memory device emulates the second emulated memory type. | 12-11-2008 |
| 20090268513 | MEMORY DEVICE WITH DIFFERENT TYPES OF PHASE CHANGE MEMORY - A memory includes a first memory device including an array of phase changing memory cells. The first memory device is of a first memory type. The integrated circuit includes a second memory device including an array of phase changing memory cells. The second memory device is of a second memory type that is different than the first memory type. The first and second memory devices are packaged together into a single memory device. | 10-29-2009 |
| 20090268532 | Systems and Methods for Writing to a Memory - An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address. | 10-29-2009 |
