Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Day, TX
Brittany Day, Colleyville, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120324624 | SCARF WITH HOOD - A scarf made from a loop of clothing material forms a channel between a front opening and a rear opening. The fastening device secures together opposing portions of a rear perimeter of the loop of clothing thereby reducing a size of the rear opening relative to a size of the front opening and forming a hood within a portion of the channel forward of the fastening device. | 12-27-2012 |
Calvin Day, Lake Jackson, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110110193 | WIRELESS EXPLORATION SEISMIC SYSTEM - Systems and methods for seismic data acquisition employing a dynamic multiplexing technique. The dynamic multiplexing technique may include advancing one or more modules in a seismic array through a multiplexing signature sequence in successive transmission periods. The multiplexing signature sequence may be random or pseudo-random. A shared multiplexing signature sequence may be used at all the modules in the seismic array. As such, modules belonging to a common collision domain may operate out of phase with respect to the shared multiplexing signature sequence. | 05-12-2011 |
| 20110158047 | SYNCHRONIZATION OF MODULES IN A WIRELESS ARRAY - Presented are systems and methods for wireless data acquisition. The wireless data acquisition may involve synchronizing modules within a data acquisition array. The synchronized data acquisition array may be used to facilitate a seismic survey. Synchronization may be facilitated by receipt of a reference time event such that a clock is synchronized based on the reference time event. | 06-30-2011 |
Chi-Ping Day, Houston, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080286860 | CANCER SPECIFIC PROMOTERS - The present invention regards cancer-specific control sequences that direct expression of a polynucleotide encoding a therapeutic gene product for treatment of the cancer. Specifically, the invention encompasses breast cancer-, prostate cancer-, and pancreatic cancer-specific control sequences. Two breast cancer-specific sequences utilize specific regions of topoisomerase IIα and transferrin receptor promoters, particularly in combination with an enhancer. The prostate cancer-specific and pancreatic cancer-specific control sequences utilize composites of tissue-specific control sequences, a two-step transcription amplification sequence, and a post-transcriptional control sequence. In more particular embodiments, these polynucleotides are administered in combination with liposomes. | 11-20-2008 |
Clifton B. Day, Weatherford, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100047010 | Self-Retaining Anti-Rotation Clip - A self-retaining anti-rotation clip for a spherical-bearing rod end has two opposing spacer plates, each spacer plate having a curved edge portion for surrounding at least a portion of a ball of the rod end. A connector plate connects the spacer plates, such that the spacer plates are spaced from each other and generally parallel to each other. Retaining means are carried on the clip and adapted for retaining each spacer plate in a position generally adjacent one side of a body of the rod end, such that the spacer plates are free from interference with the ball of the rod end. | 02-25-2010 |
| 20120251224 | Self-Retaining Anti-Rotation Clip - A self-retaining anti-rotation clip for a spherical-bearing rod end has two opposing spacer plates, each spacer plate having a curved edge portion for surrounding at least a portion of a ball of the rod end. A connector plate connects the spacer plates, such that the spacer plates are spaced from each other and generally parallel to each other. Retaining means are carried on the clip and adapted for retaining each spacer plate in a position generally adjacent one side of a body of the rod end, such that the spacer plates are free from interference with the ball of the rod end. | 10-04-2012 |
Cory D. Day, Burleson, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100263523 | RETENTION MEMBER FOR PERFORATING GUNS - A perforating gun includes a charge tube having shaped charges affixed thereto. Each shaped charge includes a radially outward pointing post adapted to receive a detonator cord. A retention member installed on the post provides a compressive force that energetically couples the detonator cord to the post. The radially outermost portion of the retention member is radially flush with or radially recessed relative to the radially outermost portion of each post. In one embodiment, the retention member has a rounded medial portion, a central opening and a pair of locking tabs that point radially inward to the central opening. Each post may include a slot for receiving the detonator cord and a circumferential groove that is adapted to receive the locking tabs. | 10-21-2010 |
Donald Day, Cypress, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110037598 | SONIC DETECTION OF FLOW STATE CHANGE FOR MEASUREMENT STATIONS - A method for audibly detecting a fluid flow state change in a flow meter pipeline. The flow state change may be identified as an upset in the normal flow state. The upset may be corrected to improve the accuracy of the flow meter. A system includes acoustic sensors mounted in the flow meter pipeline, and a computer to collect audible data from the acoustic sensors and compare the audible data to a baseline to detect an upset in the normal fluid flow state. | 02-17-2011 |
| 20110130997 | FLOW METER PROVING METHOD AND SYSTEM - A flow meter prover ( | 06-02-2011 |
Donald M. Day, Cypress, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100217531 | HYDROCARBON MEASUREMENT STATION PREVENTATIVE MAINTENANCE INTERVAL DETERMINATION - Hydrocarbon measurement station preventative maintenance interval determination. At least some of the illustrative embodiments are measurement stations configured to measure volumetric flow of hydrocarbons, where the measurement stations include a flow meter fluidly coupled to a piping system configured to carry at least one type of hydrocarbon flow, and a computer system comprising an interface device (the computer system electrically coupled to the flow meter and the computer system configured to maintain a plurality of parameters related to the volume of hydrocarbon flow in the piping). The computer system is configured to provide maintenance information for the measurement station, and the computer system provides the maintenance information at intervals determined based on constituents of hydrocarbons and based on parameters related to the volume of hydrocarbon flow in the piping. | 08-26-2010 |
Donald Merlyn Day, Cypress, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100242590 | Flow Meter and Temperature Stabilizing Cover Therefor - A flow meter and a temperature stabilizing cover for tie flow meter are disclosed. In some embodiments, the flow meter includes a spool member having a throughbore for fluids to pass therethrough, one or more transducers extending into the throughbore, and a cover disposed about the spool member and the one or more transducers. The cover includes a plurality of cover pieces fastened together. The cover pieces are formed of layers including an insulation layer, a radiant barrier, and an outer shell. The outer shell includes a material having a rigidity exceeding that of the insulation layer and that of the radiant barrier. | 09-30-2010 |
Don Rutledge Day, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080282157 | Magnifying the Text of a Link While Still Retaining Browser Function in the Magnified Display - A web browser magnifies the content of the whole page in memory and displays the relevant portion in a magnifier with hyperlinks. The web browser then maps the magnified display to the original document. Thus, manipulation of the mouse in the magnified display may result in an action with respect to the original document. The user may then select a link for navigation within the magnified display. Alternatively, the web browser may analyze the original web page and construct magnifier contents on the basis of either the document object model, extensible markup language (XML), or hypertext markup language (HTML) representation of the magnified portion. | 11-13-2008 |
| 20120131429 | Magnifying the Text of a Link While Still Retaining Browser Function in the Magnified Display - A web browser magnifies the content of the whole page in memory and displays the relevant portion in a magnifier with hyperlinks. The web browser then maps the magnified display to the original document. Thus, manipulation of the mouse in the magnified display may result in an action with respect to the original document. The user may then select a link for navigation within the magnified display. Alternatively, the web browser may analyze the original web page and construct magnifier contents on the basis of either the document object model, extensible markup language (XML), or hypertext markup language (HTML) representation of the magnified portion. | 05-24-2012 |
Dylan L. Day, Garland, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110224029 | Baseball swing development tool | 09-15-2011 |
James Alfred Day, Dallas, TX US
John Day, Arlington, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100034623 | PICKOFF MECHANISM FOR MAIL FEEDER - A pickoff system for removal of mail pieces one at a time from the end of a stack includes a pickoff belt mechanism, a sensor positioned to determine mail piece movement speed, and a measurement device determines belt movement speed during operation of the pickoff belt mechanism. A vacuum system includes a vacuum pump and a vacuum manifold positioned to apply suction to the mail piece in a direction that tends to hold the mail piece against the belt of the pickoff belt mechanism. A controller is configured to compare the belt movement speed and the mail piece movement speed during operation, and when mail piece movement speed is slower than belt movement speed, indicating slipping of the mail piece relative to the belt of the pickoff belt mechanism, the controller temporarily increases suction force applied to a mail piece being transported by the pickoff belt mechanism. | 02-11-2010 |
Matthew Daniel Day, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100306507 | OUT-OF-ORDER EXECUTION MICROPROCESSOR WITH REDUCED STORE COLLISION LOAD REPLAY REDUCTION - An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a dependency that identifies an instruction upon which the store instruction depends for its data. A register alias table (RAT), coupled to the queue of entries, is configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order. In response to encountering a load instruction the RAT determines whether sources of the load instruction used to compute its load address match the sources of the store instruction in an entry of the queue, and if so, causes the load instruction to share the dependency of the matching store instruction. | 12-02-2010 |
| 20100306508 | OUT-OF-ORDER EXECUTION MICROPROCESSOR WITH REDUCED STORE COLLISION LOAD REPLAY REDUCTION - An out-of-order execution microprocessor for reducing load instruction replay likelihood due to store collisions. A register alias table (RAT) is coupled to first and second queues of entries and generates dependencies used to determine when instructions may execute out of order. The RAT allocates an entry of the first queue and populates the allocated entry with an instruction pointer of a load instruction, when it determines that the load instruction must be replayed. The RAT allocates an entry of the second queue when it encounters a store instruction and populates the allocated entry with a dependency that identifies an instruction upon which the store instruction depends for its data. The RAT causes a subsequent instance of the load instruction to share the dependency when it encounters the subsequent instance of the load instruction and determines that its instruction pointer matches the instruction pointer of an entry of the first queue. | 12-02-2010 |
| 20100306509 | OUT-OF-ORDER EXECUTION MICROPROCESSOR WITH REDUCED STORE COLLISION LOAD REPLAY REDUCTION - An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold an instruction pointer of a load instruction and to hold information useable to identify a store instruction that caused the load instruction to be replayed on a first instance of the load instruction. A register alias table (RAT) encounters instructions in program order and generates dependencies used to determine when the instructions may execute out of program order. The RAT encounters the load instruction on a second instance, determines that the load instruction second instance instruction pointer matches the instruction pointer of an entry of the queue, and causes the load instruction on the second instance to have a dependency on the store instruction identified by the information in the matching entry. | 12-02-2010 |
| 20110035573 | OUT-OF-ORDER X86 MICROPROCESSOR WITH FAST SHIFT-BY-ZERO HANDLING - An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction. The microprocessor also includes a first execution unit configured to execute the shift instruction and to generate a second indicator that indicates whether a shift amount of the shift instruction is zero. The microprocessor also includes a second execution unit configured to receive the first and second indicators and to generate a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero. | 02-10-2011 |
Michael L. Day, Garland, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110224029 | Baseball swing development tool | 09-15-2011 |
Michael N. Day, Round Rock, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080244200 | System for Communicating Command Parameters Between a Processor and a Memory Flow Controller - A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state. | 10-02-2008 |
| 20080288757 | Communicating Instructions and Data Between a Processor and External Devices - A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state. | 11-20-2008 |
| 20090204781 | System for Limiting the Size of a Local Storage of a Processor - A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage. | 08-13-2009 |
| 20090217300 | Communicating with a Processor Event Facility - A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state. | 08-27-2009 |
Michael Norman Day, Round Rock, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080209127 | System and method for efficient implementation of software-managed cache - A system and method for an efficient implementation of a software-managed cache is presented. When an application thread executes on a simple processor, the application thread uses a conditional data select instruction for eliminating a conditional branch instruction when accessing a software-managed cache. An application thread issues a conditional data select instruction (DMA transfer) after a cache directory lookup, wherein the size of the requested data is dependent upon the outcome of the cache directory lookup. When the cache directory lookup results in a cache hit, the application thread requests a transfer of zero bits of data, which results in a DMA controller (DMAC) performing a no-op instruction. When the cache directory lookup results in a cache miss, the application thread requests a data block transfer the size of a corresponding cache line. | 08-28-2008 |
| 20080235679 | Loading Software on a Plurality of Processors - Loading software on a plurality of processors is presented. A processing unit (PU) retrieves a file from system memory and loads it into its internal memory. The PU extracts a processor type from the file's header which identifies whether the file should execute on the PU or a synergistic processing unit (SPU). If an SPU should execute the file, the PU DMA's the file to the SPU for execution. In one embodiment, the file is a combined file which includes both PU and SPU code. In this embodiment, the PU identifies one or more section headers included in the file which indicates embedded SPU code within the combined file. In this embodiment, the PU extracts the SPU code from the combined file and DMA's the extracted code to an SPU for execution. | 09-25-2008 |
| 20080263091 | Asynchronous Linked Data Structure Traversal - Asynchronously traversing a disjoint linked data structure is presented. A synergistic processing unit (SPU) includes a handler that works in conjunction with a memory flow controller (MFC) to traverse a disjoint linked data structure. The handler compares a search value with a node value, and provides the MFC with an effective address of the next node to traverse based upon the comparison. In turn, the MFC retrieves the corresponding node data from system memory and stores the node data in the SPU's local storage area. The MFC stalls processing and sends an asynchronous event interrupt to the SPU which, as a result, instructs the handler to retrieve and compare the latest node data in the local storage area with the search value. The traversal continues until the handler matches the search value with a node value or until the handler determines a failed search. | 10-23-2008 |
| 20080282064 | System and Method for Speculative Thread Assist in a Heterogeneous Processing Environment - A system and method for speculative assistance to a thread in a heterogeneous processing environment is provided. A first set of instructions is identified in a source code representation (e.g., a source code file) that is suitable for speculative execution. The identified set of instructions are analyzed to determine the processing requirements. Based on the analysis, a processor type is identified that will be used to execute the identified first set of instructions based. The processor type is selected from more than one processor types that are included in the heterogeneous processing environment. The heterogeneous processing environment includes more than one heterogeneous processing cores in a single silicon substrate. The various processing cores can utilize different instruction set architectures (ISAs). An object code representation is then generated for the identified first set of instructions with the object code representation being adapted to execute on the determined type of processor. | 11-13-2008 |
| 20080301695 | Managing a Plurality of Processors as Devices - A computer system's multiple processors are managed as devices. The operating system accesses the multiple processors using processor device modules loaded into the operating system to facilitate a communication between an application requesting access to a processor and the processor. A device-like access is determined for accessing each one of the processors similar to device-like access for other devices in the system such as disk drives, printers, etc. An application seeking access to a processor issues device-oriented instructions for processing data, and in addition, the application provides the processor with the data to be processed. The processor processes the data according to the instructions provided by the application. | 12-04-2008 |
Robert M. Day, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090130780 | SEMICONDUCTOR PROCESSING SYSTEM AND METHOD OF PROCESSING A SEMICONDUCTOR WAFER - A method of processing semiconductor wafers includes applying reactive gas through a plurality of inlets to the semiconductor wafers. The method further includes removing exhaust gas resulting from the step of applying reactive gas. The removing of the exhaust gas is through a plurality of outlets coupled to a manifold. The manifold combines the exhaust gas from the plurality of outlets. The method further includes measuring a pressure in each outlet of the plurality of outlets during the step of removing. | 05-21-2009 |
Ronald D. Day, Richardson, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110251939 | PROVISIONING SYSTEM FOR NETWORK RESOURCES - A method and system of provisioning resources installed in a network element. Resources are installed in the network element. As resources are placed into service, a notification is transmitted to the vendor. The vendor generates an invoice, and the service provider generates a purchase order. Furthermore, a capacity planning system may monitor the system as resources are placed into service. If the amount of spare resources fall below a predetermined limit, the capacity planning system may transmit a request to the vendor for the additional equipment. In this manner, resources may be installed prior to the actual need for the resources. The resources may then be paid for by the service provider as the resources are needed and placed into service, thereby enabling a risk-sharing arrangement between the service provider and the vendor. | 10-13-2011 |
Ronald Dennis Day, Garland, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080281980 | PSEUDOWIRE CIRCUIT EMULATION - A method includes establishing a first pseudowire between a first switching device and a second switching device. The method also includes receiving customer traffic that includes time division multiplexed data and formatting the time division multiplexed data as packets. The method further includes identifying a destination for the customer traffic, identifying the first pseudowire for forwarding the customer traffic and forwarding the customer traffic via the first pseudowire to the second switching device. | 11-13-2008 |
Scott Day, Dallas, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080228520 | Body Management System and Business Method - A system and business method for maintaining the health and body fitness of a client patient. The system and method are conducted by a Registered Dietitian (RD), and a technician (nurse). The RD conducts an ongoing assessment of the client to evaluate the client's progress in attaining his or her goals, as well as providing nutritional education and lifestyle modification training to ensure long-term success of the treatment. The technician conducts any tests required during the RD assessments and supervises client performance of the treatment. Various technologies are utilized to help the client achieve his or her body shaping and fitness goals. | 09-18-2008 |
William B. Day, Richmond, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20110064557 | Supply Chain Management System - In a method of managing a supply chain from a supplier to a customer by a service company that purchases a product, a plurality of costs corresponding to supply chain parameters and associated with providing a product to a customer is determined. Each of the plurality of costs is stored in a computer database and is associated with a corresponding supply chain parameter. A subset of the plurality of costs is retrieved from the computer database in response to a supply event relative to the product. A total cost for each of a plurality of supply chain permutations is calculated. Each of the plurality of supply chain permutations includes a different combination of supply chain parameters in the supply chain. The supply chain permutation having a lowest total cost is selected. The customer is supplied with the product by employing the selected supply chain permutations. | 03-17-2011 |
| 20110066576 | Supply Chain Management System - In a method of managing a supply chain from a supplier to a customer by a service company that purchases a product, a plurality of costs corresponding to supply chain parameters and associated with providing a product to a customer is determined. Each of the plurality of costs is stored in a computer database and is associated with a corresponding supply chain parameter. A subset of the plurality of costs is retrieved from the computer database in response to a supply event relative to the product. A total cost for each of a plurality of supply chain permutations is calculated. Each of the plurality of supply chain permutations includes a different combination of supply chain parameters in the supply chain. The supply chain permutation having a lowest total cost is selected. The customer is supplied with the product by employing the selected supply chain permutations. | 03-17-2011 |