Patent application number | Description | Published |
20110110193 | WIRELESS EXPLORATION SEISMIC SYSTEM - Systems and methods for seismic data acquisition employing a dynamic multiplexing technique. The dynamic multiplexing technique may include advancing one or more modules in a seismic array through a multiplexing signature sequence in successive transmission periods. The multiplexing signature sequence may be random or pseudo-random. A shared multiplexing signature sequence may be used at all the modules in the seismic array. As such, modules belonging to a common collision domain may operate out of phase with respect to the shared multiplexing signature sequence. | 05-12-2011 |
20110158047 | SYNCHRONIZATION OF MODULES IN A WIRELESS ARRAY - Presented are systems and methods for wireless data acquisition. The wireless data acquisition may involve synchronizing modules within a data acquisition array. The synchronized data acquisition array may be used to facilitate a seismic survey. Synchronization may be facilitated by receipt of a reference time event such that a clock is synchronized based on the reference time event. | 06-30-2011 |
20130135968 | Synchronization of Modules in a Wireless Array - Presented are systems and methods for wireless data acquisition. The wireless data acquisition may involve synchronizing modules within a data acquisition array. The synchronized data acquisition array may be used to facilitate a seismic survey. Synchronization may be facilitated by receipt of a reference time event such that a clock is synchronized based on the reference time event. | 05-30-2013 |
20130148469 | WIRELESS EXPLORATION SEISMIC SYSTEM - Systems and methods for seismic data acquisition employing a dynamic multiplexing technique. The dynamic multiplexing technique may include advancing one or more modules in a seismic array through a multiplexing signature sequence in successive transmission periods. The multiplexing signature sequence may be random or pseudo-random. A shared multiplexing signature sequence may be used at all the modules in the seismic array. As such, modules belonging to a common collision domain may operate out of phase with respect to the shared multiplexing signature sequence. | 06-13-2013 |
20150124563 | WIRELESS EXPLORATION SEISMIC SYSTEM - Systems and methods for seismic data acquisition employing a dynamic multiplexing technique. The dynamic multiplexing technique may include advancing one or more modules in a seismic array through a multiplexing signature sequence in successive transmission periods. The multiplexing signature sequence may be random or pseudo-random. A shared multiplexing signature sequence may be used at all the modules in the seismic array. As such, modules belonging to a common collision domain may operate out of phase with respect to the shared multiplexing signature sequence. | 05-07-2015 |
Patent application number | Description | Published |
20100047010 | Self-Retaining Anti-Rotation Clip - A self-retaining anti-rotation clip for a spherical-bearing rod end has two opposing spacer plates, each spacer plate having a curved edge portion for surrounding at least a portion of a ball of the rod end. A connector plate connects the spacer plates, such that the spacer plates are spaced from each other and generally parallel to each other. Retaining means are carried on the clip and adapted for retaining each spacer plate in a position generally adjacent one side of a body of the rod end, such that the spacer plates are free from interference with the ball of the rod end. | 02-25-2010 |
20120251224 | Self-Retaining Anti-Rotation Clip - A self-retaining anti-rotation clip for a spherical-bearing rod end has two opposing spacer plates, each spacer plate having a curved edge portion for surrounding at least a portion of a ball of the rod end. A connector plate connects the spacer plates, such that the spacer plates are spaced from each other and generally parallel to each other. Retaining means are carried on the clip and adapted for retaining each spacer plate in a position generally adjacent one side of a body of the rod end, such that the spacer plates are free from interference with the ball of the rod end. | 10-04-2012 |
20130105636 | Rotor System Anti-Rotation Wear Protector | 05-02-2013 |
20130168492 | Adjustable Pitch Link - According to one embodiment, a pitch link includes a first link, a second link coupled to a first end of the first link, a third link coupled to a second end of the first link opposite the first end, and a first bearing housing having a first bearing and a second bearing housing having a second bearing. The first bearing housing is removably coupled to the second link. The second link separates the first bearing housing from the first link. The second bearing housing is removably coupled to the third link. The third link separates the second bearing housing from the first link. | 07-04-2013 |
Patent application number | Description | Published |
20140039138 | Catalysts Comprising Salan Ligands - Catalysts comprising salan ligands with carbazole moieties. Also, catalyst systems comprising the catalyst and an activator; methods to prepare the ligands, catalysts and catalyst systems; processes to polymerize olefins using the catalysts and/or catalyst systems; and the olefin polymers prepared according to the processes. | 02-06-2014 |
20140039139 | Nonsymmetric Catalysts Comprising Salan Ligands - Catalysts comprising a non-symmetrical Salan ligand with a carbazole moiety. Also disclosed are catalyst systems comprising the catalyst and an activator; methods to prepare the ligands, catalysts and catalyst systems; processes to polymerize olefins using the catalysts and/or catalyst systems; and the olefin polymers prepared according to the processes. | 02-06-2014 |
20140039141 | Halogenated Catalysts Comprising Salan Ligands - Catalysts comprising a halogenated Salan ligand. Also disclosed are catalyst systems comprising the catalyst and an activator; methods to prepare the ligands, catalysts and catalyst systems; processes to polymerize olefins using the catalysts and/or catalyst systems; and the olefin polymers prepared according to the processes. | 02-06-2014 |
20140121325 | Propylene Copolymer Compositions and Processes to Produce Them - This invention relates to a process for producing propylene-based in-reactor compositions comprising: (a) contacting propylene and from about 0 wt % to 10 wt % C | 05-01-2014 |
20140121341 | Supported Metallocene Catalyst Systems and Methods of Preparation Thereof - This invention relates to a process to produce a supported metallocene catalyst system, the process comprising: (i) contacting a support material with an alkyl aluminum compound to provide an alkyl aluminum treated support material; wherein the alkyl aluminum compound is represented by the formula: R | 05-01-2014 |
20140128557 | Supported Salan Catalysts - Supported Salan catalysts, a process comprising contacting one or more olefins with a catalyst system comprising an activator and a Salan catalyst disposed on a support, and polymers produced by the process. | 05-08-2014 |
20140179862 | Metal Polymeryls and the Polymer Solubilized Surfaces Derived Therefrom - Disclosed herein are certain propylene-based metal polymerals and their use in modifying surfaces, and, in general, metal polymerals used in modifying surfaces. In one aspect is a metal polymeryl comprising compounds having the general formula: MR | 06-26-2014 |
20140275454 | Diphenylamine salan catalyst - Catalysts comprising Salan ligands with bridged or unbridged diphenyl amine moieties. Also, catalyst systems comprising the catalyst and an activator; methods to prepare the ligands, catalysts and catalyst systems; processes to polymerize olefins using the catalysts and/or catalyst systems; and the olefin polymers prepared according to the processes. | 09-18-2014 |
20140378633 | Long-Bridged Salen Catalyst - Catalysts comprising long-bridged salen ligands comprising an imino-phenylene-alkylene-imino or an imino-napthalenylene-alkylene-imino bridged salen compound. Also, catalyst systems comprising the catalyst and an activator; methods to prepare the ligands, catalysts and catalyst systems; processes to polymerize olefins using the catalysts and/or catalyst systems; and the olefin polymers prepared according to the processes. | 12-25-2014 |
20150025205 | Metallocenes and Catalyst Compositions Derived Tehrefrom - This invention relates to a novel group 2, 3 or 4 transition metal metallocene catalyst compound that is asymmetric having two non-identical indenyl ligands with substitution at R | 01-22-2015 |
20150025206 | Metallocenes and Catalyst Compositions Derived Therefrom - This invention relates to a novel group 2, 3 or 4 transition metal metallocene catalyst compound having two indenyl ligands with identical substitution including, for example, cyclopropyl groups and substituted phenyl groups at the 2 and 4 positions of the catalyst, respectively, where the substituents are at the 3′ and 5′ positions of the phenyl groups. | 01-22-2015 |
20150119537 | Processes Using Staged Hydrogen Addition - This invention relates to processes using staged hydrogen addition in propylene polymerization. Using this process, broad/bi-modal MWD iPP with excellent stiffness properties and melt flow rates were produced. | 04-30-2015 |
20150119540 | Novel Aluminum Alkyl With C5 Cyclic and Pendent Olefin Polymerization Catalyst - This invention relates to organoaluminum compounds, to organoaluminum activator systems, preferably supported, to polymerization catalyst systems containing these activator systems and to polymerization processes utilizing the same. In particular, this invention relates to catalyst systems comprising an ion-exchange layered silicate, an organoaluminum compound, and a metallocene. | 04-30-2015 |
20150158958 | Polyalphaolefins Prepared Using Modified Salan Catalyst Compounds - Polyalphaolefins and Salan catalysts, catalyst systems, and processes to produce the polyalphaolefins. Also disclosed are high-viscosity index polyalphaolefins and processes for producing them. | 06-11-2015 |
20150183893 | Bridged Bis(Indenyl) Transitional Metal Complexes, Production, and Use Thereof - The invention relates to a novel group bridged metallocene transition metal complexes, wherein the complex includes at least one indenyl ligand substituted at the 4-position with a phenyl group, the 4-phenyl group being preferably substituted at the 3′, 4′, and 5′ positions with particular combinations of substituents, particularly wherein the 4′-substituent is a group of the formula (XR′ | 07-02-2015 |
20150291710 | Vinyl Terminated Macromonomers - Polymers produced by a process comprising contacting one or more olefins with a catalyst system comprising an activator and a Salan catalyst disposed on a support. | 10-15-2015 |
Patent application number | Description | Published |
20100306507 | OUT-OF-ORDER EXECUTION MICROPROCESSOR WITH REDUCED STORE COLLISION LOAD REPLAY REDUCTION - An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a dependency that identifies an instruction upon which the store instruction depends for its data. A register alias table (RAT), coupled to the queue of entries, is configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order. In response to encountering a load instruction the RAT determines whether sources of the load instruction used to compute its load address match the sources of the store instruction in an entry of the queue, and if so, causes the load instruction to share the dependency of the matching store instruction. | 12-02-2010 |
20100306508 | OUT-OF-ORDER EXECUTION MICROPROCESSOR WITH REDUCED STORE COLLISION LOAD REPLAY REDUCTION - An out-of-order execution microprocessor for reducing load instruction replay likelihood due to store collisions. A register alias table (RAT) is coupled to first and second queues of entries and generates dependencies used to determine when instructions may execute out of order. The RAT allocates an entry of the first queue and populates the allocated entry with an instruction pointer of a load instruction, when it determines that the load instruction must be replayed. The RAT allocates an entry of the second queue when it encounters a store instruction and populates the allocated entry with a dependency that identifies an instruction upon which the store instruction depends for its data. The RAT causes a subsequent instance of the load instruction to share the dependency when it encounters the subsequent instance of the load instruction and determines that its instruction pointer matches the instruction pointer of an entry of the first queue. | 12-02-2010 |
20100306509 | OUT-OF-ORDER EXECUTION MICROPROCESSOR WITH REDUCED STORE COLLISION LOAD REPLAY REDUCTION - An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold an instruction pointer of a load instruction and to hold information useable to identify a store instruction that caused the load instruction to be replayed on a first instance of the load instruction. A register alias table (RAT) encounters instructions in program order and generates dependencies used to determine when the instructions may execute out of program order. The RAT encounters the load instruction on a second instance, determines that the load instruction second instance instruction pointer matches the instruction pointer of an entry of the queue, and causes the load instruction on the second instance to have a dependency on the store instruction identified by the information in the matching entry. | 12-02-2010 |
20110035573 | OUT-OF-ORDER X86 MICROPROCESSOR WITH FAST SHIFT-BY-ZERO HANDLING - An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction. The microprocessor also includes a first execution unit configured to execute the shift instruction and to generate a second indicator that indicates whether a shift amount of the shift instruction is zero. The microprocessor also includes a second execution unit configured to receive the first and second indicators and to generate a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero. | 02-10-2011 |
20150347140 | PROCESSOR THAT LEAPFROGS MOV INSTRUCTIONS - A processor performs out-of-order execution of a first instruction and a second instruction after the first instruction in program order, the first instruction includes source and destination indicators, the source indicator specifies a source of data, the destination indicator specifies a destination of the data, the first instruction instructs the processor to move the data from the source to the destination, the second instruction specifies a source indicator that specifies a source of data. A rename unit updates the second instruction source indicator with the first instruction source indicator if there are no intervening instructions that write to the source or to the destination of the first instruction and the second instruction source indicator matches the first instruction destination indicator. | 12-03-2015 |
20160098277 | COMPRESSING INSTRUCTION QUEUE FOR A MICROPROCESSOR - A compressing instruction queue for a microprocessor including a queue and redirect logic. The queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the queue without leaving unused storage locations and beginning at a first available storage location in the queue. The redirect logic performs redirection and compression to eliminate empty locations or holes in the queue and to reduce the number of write ports interfaced with each storage location of the queue. | 04-07-2016 |
Patent application number | Description | Published |
20080244200 | System for Communicating Command Parameters Between a Processor and a Memory Flow Controller - A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state. | 10-02-2008 |
20080288757 | Communicating Instructions and Data Between a Processor and External Devices - A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state. | 11-20-2008 |
20090204781 | System for Limiting the Size of a Local Storage of a Processor - A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage. | 08-13-2009 |
20090217300 | Communicating with a Processor Event Facility - A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state. | 08-27-2009 |
Patent application number | Description | Published |
20080209127 | System and method for efficient implementation of software-managed cache - A system and method for an efficient implementation of a software-managed cache is presented. When an application thread executes on a simple processor, the application thread uses a conditional data select instruction for eliminating a conditional branch instruction when accessing a software-managed cache. An application thread issues a conditional data select instruction (DMA transfer) after a cache directory lookup, wherein the size of the requested data is dependent upon the outcome of the cache directory lookup. When the cache directory lookup results in a cache hit, the application thread requests a transfer of zero bits of data, which results in a DMA controller (DMAC) performing a no-op instruction. When the cache directory lookup results in a cache miss, the application thread requests a data block transfer the size of a corresponding cache line. | 08-28-2008 |
20080235679 | Loading Software on a Plurality of Processors - Loading software on a plurality of processors is presented. A processing unit (PU) retrieves a file from system memory and loads it into its internal memory. The PU extracts a processor type from the file's header which identifies whether the file should execute on the PU or a synergistic processing unit (SPU). If an SPU should execute the file, the PU DMA's the file to the SPU for execution. In one embodiment, the file is a combined file which includes both PU and SPU code. In this embodiment, the PU identifies one or more section headers included in the file which indicates embedded SPU code within the combined file. In this embodiment, the PU extracts the SPU code from the combined file and DMA's the extracted code to an SPU for execution. | 09-25-2008 |
20080263091 | Asynchronous Linked Data Structure Traversal - Asynchronously traversing a disjoint linked data structure is presented. A synergistic processing unit (SPU) includes a handler that works in conjunction with a memory flow controller (MFC) to traverse a disjoint linked data structure. The handler compares a search value with a node value, and provides the MFC with an effective address of the next node to traverse based upon the comparison. In turn, the MFC retrieves the corresponding node data from system memory and stores the node data in the SPU's local storage area. The MFC stalls processing and sends an asynchronous event interrupt to the SPU which, as a result, instructs the handler to retrieve and compare the latest node data in the local storage area with the search value. The traversal continues until the handler matches the search value with a node value or until the handler determines a failed search. | 10-23-2008 |
20080282064 | System and Method for Speculative Thread Assist in a Heterogeneous Processing Environment - A system and method for speculative assistance to a thread in a heterogeneous processing environment is provided. A first set of instructions is identified in a source code representation (e.g., a source code file) that is suitable for speculative execution. The identified set of instructions are analyzed to determine the processing requirements. Based on the analysis, a processor type is identified that will be used to execute the identified first set of instructions based. The processor type is selected from more than one processor types that are included in the heterogeneous processing environment. The heterogeneous processing environment includes more than one heterogeneous processing cores in a single silicon substrate. The various processing cores can utilize different instruction set architectures (ISAs). An object code representation is then generated for the identified first set of instructions with the object code representation being adapted to execute on the determined type of processor. | 11-13-2008 |
20080301695 | Managing a Plurality of Processors as Devices - A computer system's multiple processors are managed as devices. The operating system accesses the multiple processors using processor device modules loaded into the operating system to facilitate a communication between an application requesting access to a processor and the processor. A device-like access is determined for accessing each one of the processors similar to device-like access for other devices in the system such as disk drives, printers, etc. An application seeking access to a processor issues device-oriented instructions for processing data, and in addition, the application provides the processor with the data to be processed. The processor processes the data according to the instructions provided by the application. | 12-04-2008 |