| Patent application number | Description | Published |
|---|
| 20090066162 | On-chip power supply voltage regulation - An integrated circuit ( | 03-12-2009 |
| 20090138658 | Cache memory system for a data processing apparatus - A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided. | 05-28-2009 |
| 20090244971 | Memory cell structure, a memory device employing such a memory cell structure, and an integrated circuit having such a memory device - A memory cell structure for a memory device is provided, the memory cell structure comprising a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, whilst the coupling capacitor stack is connected to the floating gate node and has a second programming terminal. The coupling capacitor stack comprises at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. During a programming operation, a voltage difference is established between the first programming terminal and the second programming terminal to cause charge tunnelling to occur through the tunnelling capacitor, such that after the programming operation a charge is stored in the floating gate node. During a read operation, the read transistor is activated to produce an output signal indicative of the charge stored in the floating gate node. Such a memory cell structure is efficient in terms of area, and can be manufactured using standard CMOS logic manufacturing processes, thereby avoiding some of the complexities involved in the production of more conventional EEPROM and Flash memory devices. | 10-01-2009 |
| 20100058107 | Error recovery within processing stages of an integrated circuit - An integrated circuit includes a plurality of processing stages each including processing logic | 03-04-2010 |
| 20100194205 | Isolation circuitry and method for hiding a power consumption characteristic of an associated processing circuit - An isolation circuitry and method are provided for coupling between a power supply and processing circuitry in order to provide power to the processing circuitry whilst hiding a power consumption characteristic of that processing circuitry. The isolation circuitry comprises a plurality of sub-circuits, with each sub-circuit comprising a capacitor, a first switch configured to provide a first connection between the capacitor and the power supply, a second switch configured to provide a second connection between the capacitor and the processing circuitry, and a third switch configured to provide a third connection across the capacitor to partially discharge the capacitor. Control circuitry controls the plurality of sub-circuits, such that within each sub-circuit the first switch, second switch and third switch are placed in an active state in a repeating sequence. Each of the plurality of sub-circuits further comprises a comparator configured to place the third switch in an open state when a predetermined non-zero voltage difference across the capacitor is reached during the active state of the third switch. By such an approach, it is ensured that the voltage across the comparator at the end of the discharge operation is always the same irrespective of the voltage present at the start of the discharge operation. As a result, the power consumption characteristic of the processing circuitry is entirely hidden by the isolation circuitry. Further, the isolation circuitry of the present invention provides a particular power efficient mechanism for hiding the power consumption characteristic of the processing circuitry. | 08-05-2010 |
| 20100211719 | Crossbar circuitry and method of operation of such crossbar circuitry - Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a storage circuit programmable to store a routing value, and a transmission circuit. In a transmission mode of operation the transmission circuit is responsive to the routing value indicating that the data input path should be coupled to the data output path to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. Control circuitry is used to issue control signals to the crossbar cells, and during a configuration mode of operation the control circuitry re-utilises at least one of the data output paths to program the storage circuitry of one or more of the crossbar cells. Such a construction of crossbar circuitry provides a very regular design, with uniform delay across all paths, and which requires significantly less control lines than typical prior art crossbar designs. Such crossbar circuitry is readily scalable to form large crossbars. | 08-19-2010 |
| 20100211720 | Crossbar circuitry and method of operation of such crossbar circuitry - Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable in the presence of an asserted transmission request from the associated source circuit to operate in combination with the arbitration circuits of other crossbar cells associated with the same data output path to re-use the bit lines of the data output path to detect the presence of multiple asserted transmission requests for the same data output path. In the event of such multiple asserted transmission requests, the arbitration circuitry operates in combination with the other arbitration circuits to implement a predetermined priority scheme to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between the multiple asserted transmission requests according to the predetermined priority scheme. Such a construction of crossbar circuitry enables a very efficient resolution of conflicts to be performed, whilst providing a very regular design, with uniform delay across all paths, and which requires significantly less control lines that typical prior art crossbar designs. Such crossbar circuitry is readily scalable to form large crossbars. | 08-19-2010 |
| 20100217562 | Operating parameter control of an apparatus for processing data - An apparatus for processing data | 08-26-2010 |
| 20100220538 | Integrated circuit memory power supply - An integrated circuit memory | 09-02-2010 |
| 20100220542 | Integrated circuit memory access mechanisms - A memory cell | 09-02-2010 |
| 20100235697 | Error detection in precharged logic - An integrated circuit | 09-16-2010 |
| 20110093737 | Error recovery within processing stages of an integrated circuit - An integrated circuit includes a plurality of processing stages each including processing logic | 04-21-2011 |
| 20110107166 | Error recovery within integrated circuit - An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate. | 05-05-2011 |
| 20110126051 | Error recover within processing stages of an integrated circuit - An integrated circuit includes a plurality of processing stages each including processing logic | 05-26-2011 |
| 20110138098 | Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry - Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable to selectively modify the voltage on said plurality of bit lines in order to apply an adaptive priority scheme. | 06-09-2011 |
