| Patent application number | Description | Published |
|---|
| 20090032960 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed. | 02-05-2009 |
| 20090110878 | METHODS FOR FABRICATING SUB-RESOLUTION ALIGNMENT MARKS ON SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES INCLUDING SAME - A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed. | 04-30-2009 |
| 20090152703 | Semiconductor Components Having Through Interconnects And Backside Redistribution Conductors - A semiconductor component includes a semiconductor substrate having a circuit side with integrated circuits and substrate contacts and a back side, a plurality of through interconnects in the substrate, and redistribution conductors on the back side of the substrate. Each through interconnect includes a via aligned with a substrate contact, and a conductive layer at least partially lining the via in physical and electrical contact with the substrate contact. Each redistribution conductor is formed by a portion of the conductive layer. A system includes a supporting substrate and at least one semiconductor substrate having the through interconnects and the redistribution conductors. | 06-18-2009 |
| 20090166846 | PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS - Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device. | 07-02-2009 |
| 20090321947 | SURFACE DEPRESSIONS FOR DIE-TO-DIE INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of microelectronic dies includes a first microelectronic die, a second microelectronic die attached to the first die, and a die-to-die interconnect electrically coupling the first die with the second die. The first die includes a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression. The second die includes a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact of the first die. The die-to-die interconnect electrically couples the first metal contact of the first die with the second metal contact of the second die and includes a flowable metal layer that at least partially fills the surface depression of the first die. | 12-31-2009 |
| 20100052157 | CHANNEL FOR A SEMICONDUCTOR DIE AND METHODS OF FORMATION - In semiconductor die packaging, stereo lithography cures a material around the die such that a channel is defined in the material. The channel exposes a portion of the die surface, and the channel is closed off above the die surface. The same stereo lithography process may also be used to define an opening that exposes a through-silicon via extending from the die surface. An additional or alternative channel may be similarly defined at a side perpendicular to that surface. The die may be stacked with other die, and the stereo lithography process may occur before or after stacking. A heat sink contacting the channel may also be added. | 03-04-2010 |
| 20100284139 | System Including Semiconductor Components Having Through Interconnects And Back Side Redistribution Conductors - A system includes a supporting substrate and at least one semiconductor substrate. The semiconductor component includes a semiconductor substrate having a circuit side with integrated circuits and substrate contacts and a back side, a plurality of through interconnects in the substrate, and redistribution conductors on the back side of the substrate. Each through interconnect includes a via aligned with a substrate contact, and a conductive layer at least partially lining the via in physical and electrical contact with the substrate contact. Each redistribution conductor is formed by a portion of the conductive layer. | 11-11-2010 |
| 20100320600 | SURFACE DEPRESSIONS FOR DIE-TO-DIE INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of microelectronic dies includes a first microelectronic die, a second microelectronic die attached to the first die, and a die-to-die interconnect electrically coupling the first die with the second die. The first die includes a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression. The second die includes a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact of the first die. The die-to-die interconnect electrically couples the first metal contact of the first die with the second metal contact of the second die and includes a flowable metal layer that at least partially fills the surface depression of the first die. | 12-23-2010 |
