Patent application number | Description | Published |
20090046734 | Method for Traffic Management, Traffic Prioritization, Access Control, and Packet Forwarding in a Datagram Computer Network - The invention provides an enhanced datagram packet switched computer network. The invention processes network datagram packets in network devices as separate flows, based on the source-destination address pair in the datagram packet. As a result, the network can control and manage each flow of datagrams in a segregated fashion. The processing steps that can be specified for each flow include traffic management, flow control, packet forwarding, access control, and other network management functions. The ability to control network traffic on a per flow basis allows for the efficient handling of a wide range and a large variety of network traffic, as is typical in large-scale computer networks, including video and multimedia traffic. The amount of buffer resources and bandwidth resources assigned to each flow can be individually controlled by network management. In the dynamic operation of the network, these resources can be varied—based on actual network traffic loading and congestion encountered. The invention also teaches an enhanced datagram packet switched computer network which can selectively control flows of datagram packets entering the network and traveling between network nodes. This new network access control method also interoperates with existing media access control protocols, such as used in the Ethernet or 802.3 local area network. An aspect of the invention is that it does not require any changes to existing network protocols or network applications. | 02-19-2009 |
20090100496 | MEDIA SERVER SYSTEM - A media server system includes a switch having a volatile memory such as dynamic random access memory (DRAM), for example. The switch may be configured to store one or more formatted media content streams in large blocks within the volatile memory. The switch unit also includes a switch controller including a crossbar switch that is coupled between a plurality of network ports and the volatile memory. The switch controller may be configured to create one or more concurrent media streams from one of the one or more formatted media content streams by concurrently performing read operations to a plurality of portions of the volatile memory, and to concurrently route the one or more concurrent media streams via any of the plurality of network ports, which may provide a digital transport for conveying the one or more concurrent media streams for use by the subscriber | 04-16-2009 |
20090164754 | Hierarchical block-identified data communication for unified handling of structured data and data compression - Data transmission efficiency for structured data can be improved by representing structured data using immutable blocks. The contents of the immutable blocks can include data and/or pointers to immutable blocks. An immutable data block cannot be altered after creation of the block. When data represented as immutable blocks is transmitted from one processor to another processor, the transmitter sends block contents for blocks that have not previously been defined at the receiver, and sends block IDs (as opposed to block contents) for blocks that have previously been defined at the receiver. The systematic use of block IDs instead of block contents in transmission where possible can significantly reduce transmission bandwidth requirements. | 06-25-2009 |
20090293045 | Dynamic collection attribute-based computer programming language methods - Simplified handling of dynamic collections having a variable number of elements at run time is achieved by providing for specification of collective properties of dynamic collections by a programmer. Such collective properties are distinct from type-member properties of the collection that follow from the types and type qualifiers of its members. Preferably, such dynamic collections are attributes (i.e., members) of an application defined type. | 11-26-2009 |
20090293046 | Notification-based constraint set translation to imperative execution - A method is provided for translating sets of constraint declarations to imperative code sequences based on defining an instantiatable object per set, inserting calls to a notification callback mechanism on state modification and defining calls in the constraint context as imperative code sequences that, in response to these callbacks, take actions to maintain these constraints. | 11-26-2009 |
20100100673 | Hierarchical immutable content-addressable memory processor - Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write. | 04-22-2010 |
20100131936 | Efficient automated translation of procedures in an constraint-based programming language implemented with notification and callback - A method is provided for translating sets of constraint declarations to imperative code sequences based on defining an instantiatable object per set, inserting calls to a notification callback mechanism on state modification and defining calls in the constraint context as imperative code sequences that, in response to these callbacks, take actions to maintain these constraints. This notification and callback mechanism can also be employed in connection with external events, thereby providing for efficient implementation of event-sequenced imperative procedures in a constraint programming language. | 05-27-2010 |
20100251224 | Interpreter-based program language translator using embedded interpreter types and variables - A programming language is extended to have embedded interpretive types (EIT) that define objects and variables to be resolved at translation time. A variable or data element having a type that is one of the EITs is referred to as an embedded interpretive variable (EIV). A control construct containing an EIV is interpreted (i.e. executed) at translation time. | 09-30-2010 |
20110010347 | ITERATOR REGISTER FOR STRUCTURED MEMORY - Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain. | 01-13-2011 |
20120096221 | HIERARCHICAL IMMUTABLE CONTENT-ADDRESSABLE MEMORY PROCESSOR - Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write. | 04-19-2012 |
20120131643 | Tunneled Security Groups - A method for providing security groups based on the use of tunneling is disclosed. The method includes assigning a security group identifier (SGI) to a packet and classifying the packet based on the packet's SGI. | 05-24-2012 |
20120260238 | Efficient Automated Translation of Procedures in an Constraint-Based Programming Language Implemented with Notification and Callback - A method is provided for translating sets of constraint declarations to imperative code sequences based on defining an instantiatable object per set, inserting calls to a notification callback mechanism on state modification and defining calls in the constraint context as imperative code sequences that, in response to these callbacks, take actions to maintain these constraints. This notification and callback mechanism can also be employed in connection with external events, thereby providing for efficient implementation of event-sequenced imperative procedures in a constraint programming language. | 10-11-2012 |
20120265931 | HIERARCHICAL IMMUTABLE CONTENT-ADDRESSABLE MEMORY PROCESSOR - Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write. | 10-18-2012 |
20130024645 | STRUCTURED MEMORY COPROCESSOR - Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory. | 01-24-2013 |
20130031331 | HIERARCHICAL IMMUTABLE CONTENT-ADDRESSABLE MEMORY COPROCESSOR - Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory. | 01-31-2013 |
20130275699 | SPECIAL MEMORY ACCESS PATH WITH SEGMENT-OFFSET ADDRESSING - Memory access for accessing a memory subsystem is disclosed. An instruction is received to access a memory location through a register. A tag is detected in the register, the tag being configured to indicate which memory path to access. On the event that the tag is configured to indicate that a first memory path is used, the memory subsystem is accessed via the first memory path. In the event that the tag is configured to indicate that a second memory path is used, the memory subsystem is accessed via the second memory path. | 10-17-2013 |
20140108642 | Efficient Reliable Distributed Flow-controlled Event Propagation - Improved utilization of connections that can be either available or blocked is provided by associating an atemporal connection state with each connection. If a connection is available, messages are transmitted on the connection normally. If a connection is blocked, the atemporal connection state is updated to reflect the changes that were made but not transmitted. In this manner, a record is kept that allows correct transmission of the information when the connection comes back up. More specifically, after a connection status changes from blocked to available, recovery messages are automatically generated from the atemporal connection state and transmitted on the connection. | 04-17-2014 |
20140149656 | HIERARCHICAL IMMUTABLE CONTENT-ADDRESSABLE MEMORY PROCESSOR - Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write. | 05-29-2014 |
20140258660 | HAREWARE-SUPPORTED MEMORY TEMPORAL COPY - Providing a snapshot of a physical memory region as of a specified time includes: sending, from a first processor to a second processor, a request to generate a snapshot of the physical memory region as of the specified time; and generating, using the second processor, the snapshot of the physical memory region based at least in part on a known state of the physical memory region and log information about update activity of the physical memory region. | 09-11-2014 |
20140258777 | HARDWARE SUPPORTED MEMORY LOGGING - Logging changes to a physical memory region during a logging time interval includes: detecting a write operation to the physical memory region, wherein the write operation modifies an indirect representation that corresponds to a physical data line in the physical memory region; and recording log information associated with the write operation. | 09-11-2014 |
20140366008 | NOTIFICATION-BASED CONSTRAINT SET TRANSLATION TO IMPERATIVE EXECUTION - A method is provided for translating sets of constraint declarations to imperative code sequences based on defining an instantiatable object per set, inserting calls to a notification callback mechanism on state modification and defining calls in the constraint context as imperative code sequences that, in response to these callbacks, take actions to maintain these constraints. | 12-11-2014 |
20140379658 | Constraint-based consistency with snapshot isolation - Efficient processing of concurrent atomic transactions is provided by identifying the constraints that need to be satisfied for correct application behavior. With these constraints identified, commit processing for a transaction can then refer to the constraints to see if committing the current transaction causes a problem with the constraints. If there is a conflict with the constraints, the transaction aborts. If there is no conflict with the constraints, the transaction commits. | 12-25-2014 |
20150074339 | HYBRID MAIN MEMORY USING A FINE-GRAIN LEVEL OF REMAPPING - Accessing a hybrid memory using a translation line is disclosed. The hybrid memory comprises a first portion. The translation line maps a first physical memory address to a first line in the first portion. Said mapping provides an indication that the first line is not immediately accessible in the first portion. | 03-12-2015 |