| Patent application number | Description | Published |
|---|
| 20080222361 | PIPELINED TAG AND INFORMATION ARRAY ACCESS WITH SPECULATIVE RETRIEVAL OF TAG THAT CORRESPONDS TO INFORMATION ACCESS - A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. In some cases, phased access can be described as pipelined tag and information array access, though strictly speaking, indexing into the information array need not depend on results of the tag array access. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array. | 09-11-2008 |
| 20100207687 | CIRCUIT FOR A LOW POWER MODE - A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes. | 08-19-2010 |
| 20100306302 | TECHNIQUE FOR DETERMINING IF A LOGICAL SUM OF A FIRST OPERAND AND A SECOND OPERAND IS THE SAME AS A THIRD OPERAND - A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings. | 12-02-2010 |
| 20110066918 | SOFT ERROR CORRECTION IN A MEMORY ARRAY AND METHOD THEREOF - A memory system includes a memory array. The memory array includes a plurality of storage locations arranged in rows and columns. The memory system includes error correction circuitry that generates correct data bits from data bits of the memory array and error correction bits. The data bits received by the error correction circuitry are divided in subgroups where each subgroup of data bits is used to generate a subgroup of the correct data bits. The subgroups of data bits are stored in a row of the memory array at locations that are interleaved with each other. | 03-17-2011 |
| 20110116328 | MEMORY DEVICE AND METHOD THEREOF - An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements. | 05-19-2011 |
| 20110119672 | Multi-Core System on Chip - A multi-core system on a chip ( | 05-19-2011 |
| 20110191602 | PROCESSOR WITH SELECTABLE LONGEVITY - A processor and method has at least one processor core for processing information and receives an operating voltage for powering circuitry of the processor. A selector receives a value indicative of a temperature within the processor and receives a value from a plurality of possible longevity values that each indicates a predetermined desired longevity of valid operation of the processor. An output provides an identifier that controls at least one of an operating voltage or an operating frequency of the processor, wherein the identifier provided is at least based on the value indicative of temperature and the predetermined desired longevity. A reliability storage device coupled to the selector stores the value from the plurality of possible longevity values that each indicates the predetermined desired longevity of valid operation of the processor. | 08-04-2011 |
