| Patent application number | Description | Published |
|---|
| 20090106616 | Integrated circuit using speculative execution - An integrated circuit | 04-23-2009 |
| 20090161442 | Data Processing System - A data processing system comprising a memory array having a plurality of memory cells ( | 06-25-2009 |
| 20100064287 | Scheduling control within a data processing system - A processor | 03-11-2010 |
| 20100235697 | Error detection in precharged logic - An integrated circuit | 09-16-2010 |
| 20100299557 | Providing tuning limits for operational parameters in data processing apparatus - The application discloses a means of setting tuning limits for operational parameters in a processing stage within a data processing apparatus for processing a signal. The processing stage comprises: an input for receiving the signal, processing circuitry for processing the signal and an output for outputting the processed signal at an output time; an error detecting circuit for determining if a signal output by the processing stage between the output time and a predetermined time later does not have a stable value, the predetermined time later being before a next output time, and for signaling an error if the signal is not stable; a tuning circuit for adjusting at least one operational parameter of the processing stage; a tuning limiting circuit for providing at least one tuning limit for the tuning circuit, such that the at least one operational parameter is not adjusted beyond the corresponding at least one tuning limit, a tuning limiting circuit for providing at least one tuning limit for said tuning circuit, such that said at least one operational parameter is not adjusted beyond said corresponding at least one tuning limit, the tuning limiting circuit being configured to provide the at least one tuning limit such that a signal passing along a critical path of the processing stage tuned to the tuning limit is estimated to reach the output of the processing stage at a preset time later than the output time, the preset time being less than the predetermined time. | 11-25-2010 |
| Patent application number | Description | Published |
|---|
| 20080250271 | Error recovery following speculative execution with an instruction processing pipeline - An instruction processing pipeline | 10-09-2008 |
| 20090282281 | Low power, high reliability specific compound functional units - To prevent short path errors from occurring in systems having error detection and recovery mechanisms, functional elements are combined to form compound functional units comprising at least two evaluation stages, each evaluation stage including at least one functional element. At least one functional element includes error detection/recovery circuitry. The flow of input values to the first evaluation stage in the compound functional unit is controlled so that the input values are changed at most every second clock cycle. | 11-12-2009 |
| 20100064109 | Managing storage units in multi-core and multi-threaded systems - A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item. When later a high priority storage item is allocated to a selected entry of the storage unit, a comparison operation between the allocated high priority storage item and the indication in the history field for the block containing the selected entry is carried out, and on detection of a match condition a lock indication associated with that entry is set to inhibit further eviction of that high priority storage item. | 03-11-2010 |
| 20100134148 | Detecting transitions in circuits during periodic detection windows - Transition detection circuitry for detecting during multiple clock cycles, transitions occurring within a detection period in each of said multiple clock cycles at a plurality of nodes within a circuit is disclosed. The transition detection circuitry comprises: a clock signal generator for generating a detection clock signal from a clock signal clocking a sampling element within said circuit, said detection clock signal defining said detection period; a plurality of transition detectors for detecting transitions at respective ones of said plurality of nodes during said detection period, each of said plurality of transition detectors being clocked by said detection clock signal; and combining circuitry for combining said detected transitions output by said plurality of transition detectors to generate a composite transition detection signal. | 06-03-2010 |
| 20100232250 | Interface circuit and method for coupling between a memory device and processing circuitry - Interface circuitry is provided for coupling between a memory device and processing circuitry, the processing circuitry issuing a plurality of access signals relating to accesses to be performed in the memory device. The interface circuitry comprises write address latch circuitry for storing a write address signal, and write address decoder circuitry that is responsive to a set first enable signal to decode the write address signal provided from the write address latch circuitry. Further, read address latch circuitry is provided for storing a read address signal issued by the processing circuitry, and read address decoder circuitry is responsive to a set second enable signal for decoding the read address signal provided from the read address latch circuitry. Decoder select latch circuitry is responsive to an access type indication signal from the processing circuitry to generate the first and second enable signals in dependence on that access type indication signal. In the event of metastability occurring in the decoder select latch circuitry, the decoder select latch circuitry is arranged not to set at least the second enable signal, thereby disabling at least the read address decoder circuitry in the presence of such metastability. Such an approach prevents metastable signals being used in the arbitration of data accesses in a manner which could corrupt the state of the memory device. | 09-16-2010 |
