| Patent application number | Description | Published |
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| 20080218197 | PROGRAMMABLE LOGIC DEVICE HAVING REDUNDANCY WITH LOGIC ELEMENT GRANULARITY - A PLD having logic element row granularity redundancy is disclosed. The PLD includes a plurality of LABs arranged in an array and a plurality of horizontal and vertical inter-LAB lines interconnecting the LABs of the array. Each of the LABs further includes a predetermined number of logic elements and redundancy circuitry to replace a defective logic element with a non-defective logic element among the predetermined logic elements by shifting programming data intended to for the defective logic element to the non-defective logic element. | 09-11-2008 |
| 20080218208 | PROGRAMMABLE LOGIC DEVICE HAVING LOGIC ARRAY BLOCK INTERCONNECT LINES THAT CAN INTERCONNECT LOGIC ELEMENTS IN DIFFERENT LOGIC BLOCKS - A PLD with LAB interconnect lines that span adjacent LABs in the array and that have the ability to interconnect two logic elements in the different LABs. The PLD includes a plurality of LABs arranged in an array and a plurality of inter-LAB lines interconnecting the LABs of the array. Each of the LABs include a predetermined number of logic elements, one or more control signals distributed among the predetermined number of logic elements in the LAB, and LAB lines spanning between logic elements in different LABs in the array. In various embodiments, the LAB lines are arranged in a staggered pattern with a predetermined pitch between the lines. In other embodiments, the control signals of adjacent LABs can overlap, allowing control signals to be routed to the logic elements of adjacent LABs. | 09-11-2008 |
| 20080231316 | Distributed memory in field-programmable gate array integrated circuit devices - Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA. | 09-25-2008 |
| 20080238476 | Configurable time borrowing flip-flops - Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch. | 10-02-2008 |
| 20080263481 | APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS - A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD. | 10-23-2008 |
| 20080263490 | APPARATUS AND METHODS FOR OPTIMIZING THE PERFORMANCE OF PROGRAMMABLE LOGIC DEVICES - A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD. | 10-23-2008 |
| 20080290897 | PROGRAMMABLE LOGIC DEVICE HAVING LOGIC MODULES WITH IMPROVED REGISTER CAPABILITIES - A PLD that has more flip flops per logic module by providing more registered outputs than combinational outputs; and/or a combinational output that can drive more than one register is disclosed. The PLD includes a plurality of logic array blocks arranged in an array and a plurality of inter-logic array block lines interconnecting the logic array blocks of the array. At least one of the logic array blocks includes at least one logic module that includes a first combinational element configured to generate a first combinational output signal in response to inputs provided to the one logic module, a first register capable of being driven by the first combinational output signal and a second register capable of being driven by the first combinational output signal. The logic module therefore has more registered outputs than combinational outputs and a combinational output that can drive more then one output register. In alternative embodiments, the logic module may have one or more combinational element configured to generate one or more combinational output signals in response to inputs provided to the one logic module and a plurality of registers capable of being driven by the one or more combinational outputs signals. In these alternative embodiments, the number of registers exceeds the number of combinational output signals in the one logic module. | 11-27-2008 |
| 20090243687 | ROBUST TIME BORROWING PULSE LATCHES - Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths. | 10-01-2009 |
| 20090267643 | FLEXIBLE ADDER CIRCUITS WITH FAST CARRY CHAIN CIRCUITRY - Configurable adder circuitry is provided on an integrated circuit that includes redundant circuitry. The integrated circuit may contain nonvolatile memory and logic circuitry that produces a redundancy control signal. During manufacturing, the integrated circuitry may be tested. If a defect is identified on the integrated circuit, the redundancy control signal may be used in switching redundant circuitry into place bypassing the defect. The integrated circuit may contain an array of logic regions. Each logic region may contain adders and multiplexer circuitry for selectively combining the multiplexers to form larger adders. The multiplexer circuitry in each logic region may be controlled by propagate signals from the adders and by static redundancy control signals. | 10-29-2009 |
| 20090278566 | CONFIGURABLE TIME BORROWING FLIP-FLOPS - Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch. | 11-12-2009 |
| 20090289696 | Apparatus and Methods for Adjusting Performance of Integrated Circuits - A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit. | 11-26-2009 |
| 20090299721 | APPARATUS AND METHODS FOR MODELING POWER CHARACTERISTICS OF ELECTRONIC CIRCUITRY - Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating power consumption of a circuit in an IC includes decomposing the IC into a plurality of overlapping blocks. Each block in the plurality of blocks includes a portion of the circuitry in the IC. The method further includes estimating power consumption of each block in the plurality of blocks, and estimating power consumption of the IC based on the power consumption of the plurality of blocks. | 12-03-2009 |
| 20090315588 | VARIABLE SIZED SOFT MEMORY MACROS IN STRUCTURED CELL ARRAYS, AND RELATED METHODS - The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may have different requirements (e.g., in terms of size) for such memory blocks. For example, pre-designed macros of memory blocks may be provided and then combined as needed to provide memory blocks of various sizes. Placement constraints may be observed for certain portions of the memory circuitry (e.g., the memory core), while other portions (e.g., address predecoder circuitry, write and read data registers, etc.) may be located relatively freely. | 12-24-2009 |
| 20100060309 | MULTI-ROW BLOCK SUPPORTING ROW LEVEL REDUNDANCY IN A PLD - In a Programmable Logic Device (PLD), a multi-row block that has internal logic connections between rows has redundant internal connections between rows to replace the internal logic connections when a fault occurs. The redundant internal logic connections extend through a row, linking the row above a defective row with a row below the defective row. Elements in a multi-row block are configurable to perform a default function and a function of an element in a neighboring row, if the functions are different. | 03-11-2010 |
| 20100228806 | MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY - Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters. | 09-09-2010 |
| 20100244893 | VARIABLE SIZED SOFT MEMORY MACROS IN STRUCTURED CELL ARRAYS, AND RELATED METHODS - The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may have different requirements (e.g., in terms of size) for such memory blocks. For example, pre-designed macros of memory blocks may be provided and then combined as needed to provide memory blocks of various sizes. Placement constraints may be observed for certain portions of the memory circuitry (e.g., the memory core), while other portions (e.g., address predecoder circuitry, write and read data registers, etc.) may be located relatively freely. | 09-30-2010 |
| 20110089008 | CONFIGURABLE MULTI-GATE SWITCH CIRCUITRY - Integrated circuits with configurable multi-gate switch circuitry are provided. The switch circuitry may include switch control circuitry and an array of multi-gate switches. Each multi-gate switch may have first and second terminals, first and second gates, and a metal bridge. The metal bridge is attached to the first terminal. The metal bridge may extend over the gates and may hover above the second terminal in the off state. The metal bridge may have a tip that bends down to physically contact the second terminal in the on state. Switch control circuitry may provide row and column control signals to load desired switch states into the switch array. The switch array may be partitioned into groups of switches that form multiplexers. The multiplexers may be used in programmable circuits such as programmable logic device circuits. | 04-21-2011 |
| 20110089974 | ROBUST TIME BORROWING PULSE LATCHES - Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths. | 04-21-2011 |
| 20110102017 | CONFIGURABLE TIME BORROWING FLIP-FLOPS - Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch. | 05-05-2011 |
| 20110107290 | VARIABLE SIZED SOFT MEMORY MACROS IN STRUCTURED CELL ARRAYS, AND RELATED METHODS - The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may have different requirements (e.g., in terms of size) for such memory blocks. For example, pre-designed macros of memory blocks may be provided and then combined as needed to provide memory blocks of various sizes. Placement constraints may be observed for certain portions of the memory circuitry (e.g., the memory core), while other portions (e.g., address predecoder circuitry, write and read data registers, etc.) may be located relatively freely. | 05-05-2011 |
