| Patent application number | Description | Published |
|---|
| 20090044070 | SYSTEM AND METHOD FOR TRELLIS DECODING IN A MULTI-PAIR TRANSCEIVER SYSTEM - A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword. | 02-12-2009 |
| 20090067559 | SYSTEM AND METHOD FOR HIGH-SPEED DECODING AND ISI COMPENSATION IN A MULTI-PAIR TRANSCEIVER SYSTEM - A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero. | 03-12-2009 |
| 20100086019 | High-Speed Decoder for a Multi-Pair Gigabit Transceiver - A method and a system for providing an input signal from a multiple decision feedback equalizer to a decoder based on a tail value and a subset of coefficient values received from a decision-feedback equalizer. A set of pre-computed values based on the subset of coefficient values is generated. Each of the pre-computed values is combined with the tail value to generate a tentative sample. One of the tentative samples is selected as the input signal to the decoder. In one aspect of the system, tentative samples are saturated and then stored in a set of registers before being outputted to a multiplexer which selects one of the tentative samples as the input signal to the decoder. This operation of storing the tentative samples in the registers before providing the tentative samples to the multiplexer facilitates high-speed operation by breaking up a critical path of computations into substantially balanced first and second portions, the first portion including computations in the decision-feedback equalizer and the multiple decision feedback equalizer, the second portion including computations in the decoder. | 04-08-2010 |
| 20100208788 | SYSTEM AND METHOD FOR HIGH-SPEED DECODING AND ISI COMPENSATION IN A MULTI-PAIR TRANSCEIVER SYSTEM - A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero. | 08-19-2010 |
